VLSI architectures design for encoders of High Efficiency Video Coding (HEVC) standard

The growing popularity of high resolution video and the continuously increasing demands for high quality video on mobile devices are producing stronger needs for more efficient video encoder. Concerning these desires, HEVC, a newest video coding standard, has been developed by a joint team formed by ISO/IEO MPEG and ITU/T VCEG. Its design goal is to achieve a 50% compression gain over its predecessor H.264 with an equal or even higher perceptual video quality. Motion Estimation (ME) being as one of the most critical module in video coding contributes almost 50%-70% of computational complexity in the video encoder. This high consumption of the computational resources puts a limit on the performance of encoders, especially for full HD or ultra HD videos, in terms of coding speed, bit-rate and video quality. Thus the major part of this work concentrates on the computational complexity reduction and improvement of timing performance of motion estimation algorithms for HEVC standard. First, a new strategy to calculate the SAD (Sum of Absolute Difference) for motion estimation is designed based on the statistics on property of pixel data of video sequences. This statistics demonstrates the size relationship between the sum of two sets of pixels has a determined connection with the distribution of the size relationship between individual pixels from the two sets. Taking the advantage of this observation, only a small proportion of pixels is necessary to be involved in the SAD calculation. Simulations show that the amount of computations required in the full search algorithm is reduced by about 58% on average and up to 70% in the best case. Secondly, from the scope of parallelization an enhanced TZ search for HEVC is proposed using novel schemes of multiple MVPs (motion vector predictor) and shared MVP. Specifically, resorting to multiple MVPs the initial search process is performed in parallel at multiple search centers, and the ME processing engine for PUs within one CU are parallelized based on the MVP sharing scheme on CU (coding unit) level. Moreover, the SAD module for ME engine is also parallelly implemented for PU size of 32×32. Experiments indicate it achieves an appreciable improvement on the throughput and coding efficiency of the HEVC video encoder. In addition, the other part of this thesis is contributed to the VLSI architecture design for finding the first W maximum/minimum values targeting towards high speed and low hardware cost. The architecture based on the novel bit-wise AND scheme has only half of the area of the best reference solution and its critical path delay is comparable with other implementations. While the FPCG (full parallel comparison grid) architecture, which utilizes the optimized comparator-based structure, achieves 3.6 times faster on average on the speed and even 5.2 times faster at best comparing with the reference architectures. Finally the architecture using the partial sorting strategy reaches a good balance on the timing performance and area, which has a slightly lower or comparable speed with FPCG architecture and a acceptable hardware cost

Gender Differences in Depressive Symptoms Among HIV-Positive Concordant and Discordant Heterosexual Couples in China.

HIV seropositive individuals and their heterosexual partners/spouses, either seropositive or seronegative, are facing several mental health challenges. The objective of this study was to examine gender differences in depressive symptoms among HIV-positive concordant and HIV-discordant couples. We identified heterosexual couples from participants of a randomized controlled trial conducted in Anhui province, China. A total of 265 couples, comprising 129 HIV+ male/HIV- female couples, 98 HIV- male/HIV+ female couples, and 38 HIV-positive concordant couples, were included in the analyses. We collected data using the computer-assisted personal interview method. We used a linear mixed-effects regression model to assess whether gender differences in depressive symptoms varied across couple types. HIV-positive women reported a significantly higher level of depressive symptoms than their partners/spouses. HIV-positive women with HIV-positive partners had higher depressive symptoms than those with HIV-negative partners, whereas HIV-positive men reported similar levels of depressive symptoms regardless of their partners' serostatus. Among the concordant couples, those with the highest annual family income showed the greatest gender differences in depressive symptoms. We suggest that family interventions should be gender- and couple-type specific and that mental health counseling is warranted not only for HIV-positive women but also for HIV-negative women in an HIV-affected relationship

A Span-Extraction Dataset for Chinese Machine Reading Comprehension

Machine Reading Comprehension (MRC) has become enormously popular recently and has attracted a lot of attention. However, the existing reading comprehension datasets are mostly in English. In this paper, we introduce a Span-Extraction dataset for Chinese machine reading comprehension to add language diversities in this area. The dataset is composed by near 20,000 real questions annotated on Wikipedia paragraphs by human experts. We also annotated a challenge set which contains the questions that need comprehensive understanding and multi-sentence inference throughout the context. We present several baseline systems as well as anonymous submissions for demonstrating the difficulties in this dataset. With the release of the dataset, we hosted the Second Evaluation Workshop on Chinese Machine Reading Comprehension (CMRC 2018). We hope the release of the dataset could further accelerate the Chinese machine reading comprehension research. Resources are available: https://github.com/ymcui/cmrc2018Comment: 6 pages, accepted as a conference paper at EMNLP-IJCNLP 2019 (short paper

An analysis and optimization of partial stress of temporary blocks in the process of bridge construction using long-span PC continuous beams

Prestressed concrete bridge, made as rigid-frame-continuous combination beams, has a specific structure and method of construction. Continuous beams, bridge piers and beams in particular need to be consolidated temporarily in the process of construction. The structure system of a bridge transforms after the construction of beams has finished. Based on the example of the West River Bridge, this paper discusses the analysis and simulation method of bridge construction with prestressed concrete continuous beams under temporary consolidation. In the condition of the largest cantilever, we calculated and got three-dimensional stress state and deformation of a temporary concrete block, using a finite element model of continuous beam zero block, which was established by methods described in the paper. Then, we analysed the specific location where the stress exceeded the prescribed value. We tried to adjust it, and finally found out an optimal method of adjustment. By adjusting the vertical prestress and the size of a temporary block, this model can simulate stress/deformation state of a temporary block fairly accurately, ensure the construction of continuous beams bridge to be safe in the condition of the largest cantilever

A Parallel Radix-Sort-Based VLSI Architecture for Finding the First W Maximum/Minimum Values

Very-large-scale integration (VLSI) architectures for finding the first W (W>2) maximum (or minimum) values are required in the implementation of several applications such as nonbinary low-density-parity-check decoders, K-best multiple-input–multiple-output (MIMO) detectors, and turbo product codes. In this brief, a parallel radix-sort-based VLSI architecture for finding the first W maximum (or minimum) values is proposed. The described architecture, called Bit-Wise-And (BWA) architecture, relies on analyzing input data from the most significant bit to the least significant one, with very simple logic circuits. One key feature in the BWA architecture is its high level of scalability, which enables the adoption of this solution in a large spectrum of applications, corresponding to large ranges for both W and the size of the input data set. Experimental results, achieved by implementing the proposed architecture on a high-speed 90-nm CMOS standard-cell technology, show that BWA architecture requires significantly less area than other solutions available in the literature, i.e., less than or about 50% in all the considered cases and about 50% in the worst case. Moreover, the BWA architecture exhibits the lowest area–delay product among almost all considered cases

Back-action Induced Non-equilibrium Effect in Electron Charge Counting Statistics

We report our study of the real-time charge counting statistics measured by a quantum point contact (QPC) coupled to a single quantum dot (QD) under different back-action strength. By tuning the QD-QPC coupling or QPC bias, we controlled the QPC back-action which drives the QD electrons out of thermal equilibrium. The random telegraph signal (RTS) statistics showed strong and tunable non-thermal-equilibrium saturation effect, which can be quantitatively characterized as a back-action induced tunneling out rate. We found that the QD-QPC coupling and QPC bias voltage played different roles on the back-action strength and cut-off energy.Comment: 4 pages, 4 figures, 1 tabl