An antenna switching based NOMA scheme for IEEE 802.15.4 concurrent transmission

This paper introduces a Non-Orthogonal Multiple Access (NOMA) scheme to support concurrent transmission of multiple IEEE 802.15.4 packets. Unlike collision avoidance Multiple Access Control (MAC), concurrent transmission supports Concurrent-MAC (C-MAC) where packet collision is allowed. The communication latency can be reduced by C-MAC because a user can transmit immediately without waiting for the completion of other users’ transmission. The big challenge of concurrent transmission is that error free demodulation of multiple collided packets hardly can be achieved due to severe Multiple Access Interference (MAI). To improve the demodulation performance with MAI presented, we introduce an architecture with multiple switching antennas sharing a single analog transceiver to capture spatial character of different users. Successive Interference Cancellation (SIC) algorithm is designed to separate collided packets by utilizing the spatial character. Simulation shows that at least five users can transmit concurrently to the SIC receiver equipped with eight antennas without sacrificing Packet Error Rate

Openwifi : a free and open-source IEEE802.11 SDR implementation on SoC

Open source Software Defined Radio (SDR) project, such as srsLTE and Open Air Interface (OAI), has been widely used for 4G/5G research. However the SDR implementation of the IEEE802.11 (Wi-Fi) is still difficult. The Wi-Fi Short InterFrame Space (SIFS) requires acknowledgement (ACK) packet being sent out in 10μs/16μs(2.4 GHz/5GHz) after receiving a packet successfully, thus the Personal Computer (PC) based SDR architecture hardly can be used due to the latency (≥100μs) between PC and Radio Frequency (RF) front-end. Researchers have to do simulation, hack a commercial chip or buy an expensive reference design to test their ideas. To change this situation, we have developed an open-source full-stack IEEE802.11a/g/n SDR implementation — openwifi. It is based on Xilinx Zynq Systemon-Chip (SoC) that includes Field Programmable Gate Array (FPGA) and ARM processor. With the low latency connection between FPGA and RF front-end, the most critical SIFS timing is achieved by implementing Physical layer (PHY) and low level Media Access Control (low MAC) in FPGA. The corresponding driver is implemented in the embedded Linux running on the ARM processor. The driver instantiates Application Programming Interfaces (APIs) defined by Linux mac80211 subsystem, which is widely used for most SoftMAC Wi-Fi chips. Researchers could study and modify openwifi easily thanks to the modular design. Compared to PC based SDR, the SoC is also a better choice for portable and embedded scenario

An Analysis Report of College English Classroom Teaching in the Grading Model

Based on data collected from Grade 2015 and Grade 2016, the present article mainly analyzes current situations of the grading model being implemented in a west provincial university. As frontline teachers, we cannot participate in the decision of which model to use, but can try our best to conduct frequent reflection and make necessary changes in classroom teaching for the good of college students’ achievements in English course. Due mostly to the limitations of one teacher’s first-hand experience, the research seems hard to hold water, and more are expected to participate in this topic. Only by means of active exploration and generous contributions from all teachers and educators concerned, will China College English be improved and productive in developing all-around talents needed for the realization of Chinese dreams

An approach to achieve zero turnaround time in TDD operation on SDR front-end

Thanks to the digitization and softwarization of radio communication, the development cycle of new radio technologies can be significantly accelerated by prototyping on software-defined radio (SDR) platforms. However, a slow turnaround time (TT) of the front-end of an SDR for switching from receiving mode to transmitting mode or vice versa, are jeopardizing the prototyping of wireless protocols, standards, or systems with stringent latency requirements. In this paper, a novel solution called BaseBand processing unit operating in Half Duplex mode and analog Radio Frequency front-end operating in Full Duplex mode, BBHD-RFFD, is presented to reduce the TT on SDR. A prototype is realized on the widely adopted AD9361 radio frequency frontend to prove the validity of the proposed solution. Experiments unveil that for any type of application, the TT in time division duplex (TDD) operation mode can be reduced to zero by the BBHD-RFFD approach, with negligible impact on the communication system in terms of receiver sensitivity. The impact is measured for an in-house IEEE 802.15.4 compliant transceiver. When compared against the conventional TDD approach, only a 7.5-dB degradation is observed with the BBHD-RFFD approach. The measured sensitivity of -91 dBm is still well above the minimum level (i.e., -85 dBm at 2.4 GHz) defined by the IEEE 802.15.4 standard

CMCVT : a concurrent multi-channel virtual transceiver

State-of-the-art wireless Gateways (GW) used in Internet of Things (IoT) offer a single channel radio link, which limits the capabilities of the IoT network controlled by the GW, as the GW can only use a single channel at a time to communicate with the end-device(s). The quality of service (e.g., aggregate throughput, latency) offered by a single channel GW could be substantially improved by employing a multi-channel transceiver, which is capable of transmitting/receiving data on different radio channels simultaneously, particularly for larger wireless networks. However, current solutions available in both research and commercial communities only offer multi-channel receiver capabilities, and do not incorporate the multi-channel transmitter part. In addition, in terms of implementation, these multi-channel receivers duplicate single-channel hardware functionality. In this paper, for the first time, a novel concurrent multi-channel virtual transceiver is introduced. The virtual transceiver offers multi-channel capabilities and uses the same single-hardware hardware implementation for the Physical (PHY) layer by employing the virtualization technique. This new virtual transceiver concept is demonstrated for an IEEE 802.15.4 based 8 x 8 channel transceiver, implemented on an Field Programmable Gate Array (FPGA) of a modern Software Defined Radio and is compared with the existing duplication approach. The duplication approach consumes 9008 LUTs, and 12120 FFs, whereas the proposed approach occupies only 2959 LUTs and 2105 FFs, saving 67.15% LUTs and 82.63% FFs in comparison with the duplication approach. The experimental results reveal that the virtual transceiver provides the same performance (e.g., receiver sensitivity of -98.5dBm) as the transceiver achieved by duplicating the PHY layers but consumes much less hardware resources. (C) 2020 The Authors. Published by Elsevier GmbH

Accelerating FPGA-Based Wi-Fi Transceiver Design and Prototyping by High-Level Synthesis

Field-Programmable Gate Array (FPGA)-based Software-Defined Radio (SDR) is well-suited for experimenting with advanced wireless communication systems, as it allows to alter the architecture promptly while obtaining high performance. However, programming the FPGA using a Hardware Description Language (HDL) is a time-consuming task for FPGA developers and difficult for software developers, which limits the potential of SDR. High-Level Synthesis (HLS) tools aid the designers by allowing them to program on a higher layer of abstraction. However, if not carefully designed, it may lead to a degradation in computing performance or significant increase in resource utilization. This work shows that it is feasible to design modern Orthogonal Frequency Division Multiplex (OFDM) baseband processing modules like channel estimation and equalization using HLS without sacrificing performance and to integrate them in an HDL design to form a fully-operational FPGA-based Wi-Fi (IEEE 802.11a/g/n) transceiver. Starting from no HLS experience, a design with minor overhead in terms of latency and resource utilization as compared to the HDL approach was created in less than one month. We show the readability of the sequential logic as coded in HLS, and discuss the lessons learned from the approach taken and the benefits it brings for further design and experimentation. The FPGA design generated by HLS was verified to be bit-true with its MATLAB implementation in simulation. Furthermore, we show its practical performance when deployed on a System-on-Chip (SoC)-based SDR using a professional wireless connectivity tester.Comment: 7 pages, extended version of poster accepted at FCCM 202

Interactive Digital Entertainment: A New Direction for Information Systems Research

Interactive digital entertainment (IDE) includes Internet-based gaming, wireless gaming, online discussion clubs for sports or music fans, and any other form of consumer-to-consumer (C2C) entertainment that involves human-computer or human-human interaction via the Internet (or wireless). According to a recent article in Financial Times (Foremski et al. 2003), the corporate spending on IT has become stagnant in recent years while the market for consumer technologies maintains a strong growth trend. IDE is an especially bright spot among the fastest growing business models targeting the consumer market (Black 2003). For instance, 5 years into the U.S. market, Sony’s popular online game, EverQuest, has already attracted 400,000 subscribers and is expected to earn Sony up to $500 million in 8 years (Hardy 2004). This stellar growth is not without problems: many early business developments on IDE, even the ones from the largest and most experienced game developers such as Electronic Arts, have faltered. These failures can cost IDE companies tens of millions of dollars (Hardy 2004). Past failures and successes seem to suggest that the success of IDE depends not only on solid IDE systems development that deliver competitive technological performance and enduring entertainment content, but also on deep compre- hension of IDE systems adoption and usage by consumers who ultimately decide the fate of any IDE product. Newer generations of IDE systems, such as World of Warcrafts from Blizzard Entertainment, have greatly improved their technological performance by tapping into the latest computing and communication technologies. Nevertheless, huge gaps exist in our understanding of how to make IDE systems and content more entertaining while controlling the development cost. Furthermore, IDE providers often fail to capitalize on their investment. For instance, Internet-based board games, while popular, have contributed little profit to vendors as consumers generally shun fee-based games. Finally, there is a lack of understanding about the roles of IDE com- munities in IDE markets. After all, IDE users typically interact with a community of peers, a feature that distinguish IDEs from stand-alone entertainment or TV-based entertainment. The purpose of this panel is to bring together industry experts and IS researchers to (1) introduce the development of the IDE industry to an IS audience and discuss the problems encountered in this development process, (2) lay out an array of new research venues around IDE systems and communities, and (3) discuss the impact of IDE on individuals and the society