53 research outputs found

    Analysis and design of reliable mixed-signal CMOS circuits

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    Facing the constantly increasing reliability challenges under technology scaling, the topics in IC reliability technique have been receiving serious attention during recent years. In this work, based on the understanding of existing physical failure models that have been concentrating on the pre-fab circuits, a set of revised models for major failure mechanisms such as electromigration, hot-carrier, and gate oxide wear-out are created. Besides the modeling of degradation behaviors for circuits in design phase, these models tend to deal with the post-fab device characteristics with the presence of physical defects. In addition, the simulation work has been taken from device level to circuit level hierarchically, presenting the evaluation of circuit level reliability such as degradations of circuit level specs and circuit lifetime prediction. For post-fab ICs under electromigration, the expected circuit lifetime is calculated based on statistical processes and the probability theory. By incorporating all physics-of-failure models and applying circuit level simulation approaches, an IC reliability simulator called ARET (ASIC reliability evaluation tool) has been developed. Besides the reliability evaluation, the reliability hotspot identification function is developed in ARET, which is a key step for conducting IC local design-for-reliability approaches. ARET has been calibrated with a series of stress tests conducted at The Boeing Company. Design-for-reliability (DFR) is a very immature technical area, which has been becoming critical with the continuously shrinking reliability safety margin. A novel concept, local design-for-reliability is proposed in this work. This DFR technique is closely based on reliability simulation and hotspot identification. By redesigning the circuit locally around reliability hotspots, this DFR approach offers the overall reliability improvement with the maintained circuit performance. Various DFR algorithms are developed for different circuit situations. The experiments on designed and benchmark circuits have shown that significant circuit reliability improvements can be obtained without compromising performance by applying these DFR algorithms.Ph.D.Committee Chair: Chatterjee, Abhijit; Committee Member: Keezer, David; Committee Member: May, Gary; Committee Member: Singh, Adit; Committee Member: Swaminathan, Madhava

    IL-10 family cytokines in chronic rhinosinusitis with nasal polyps: From experiments to the clinic

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    Chronic rhinosinusitis with nasal polyps (CRSwNP) is considered a nasal sinus inflammatory disease that can be dominated by immune cells and cytokines. IL-10 family cytokines exert essential functions in immune responses during infection and inflammation. Recently, the understanding of the roles of the IL-10 family in CRSwNP is being reconsidered. IL-10 family members are now considered complex cytokines that are capable of affecting epithelial function and involved in allergies and infections. Furthermore, the IL-10 family responds to glucocorticoid treatment, and there have been clinical trials of therapies manipulating these cytokines to remedy airway inflammatory diseases. Here, we summarize the recent progress in the understanding of IL-10 family cytokines in CRSwNP and suggest more specific strategies to exploit these cytokines for the effective treatment of CRSwNP.</jats:p

    An inverter chain with parallel output nodes for eliminating single-event transient pulse

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    A single event upset tolerant latch with parallel nodes

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    Flexible Wearable Humidity Sensor Based on Nanodiamond With Fast Response

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