Bending crystals: Emergence of fractal dislocation structures

We provide a minimal continuum model for mesoscale plasticity, explaining the cellular dislocation structures observed in deformed crystals. Our dislocation density tensor evolves from random, smooth initial conditions to form self-similar structures strikingly similar to those seen experimentally - reproducing both the fractal morphologies and some features of the scaling of cell sizes and misorientations analyzed experimentally. Our model provides a framework for understanding emergent dislocation structures on the mesoscale, a bridge across a computationally demanding mesoscale gap in the multiscale modeling program, and a new example of self-similar structure formation in non-equilibrium systems.Comment: 4 pages, 4 figures, 5 movies (They can be found at http://www.lassp.cornell.edu/sethna/Plasticity/SelfSimilarity.html .) In press at Phys. Rev. Let

A Low-Jitter 8-GHz RO-Based ADPLL With PVT-Robust Replica-Based Analog Closed Loop for Supply Noise Compensation

IEEEThis article presents a ring oscillator (RO)-based all-digital phase-locked loop (ADPLL) that is implemented with a high-gain analog closed loop for supply noise compensation (ACSC). The ACSC not only allows high-frequency oscillation of the RO but also is robust over process, voltage, and temperature (PVT) variations thanks to its replica-based configuration. Moreover, a comprehensive analysis of the noise contribution of the ACSC is conducted for the ADPLL to retain its low-jitter output. Implemented in 40-nm CMOS technology, the ADPLL, with a 1.1-V supply, achieves an rms jitter of 289 fs at 8 GHz without any injected supply noise. Under a 20-m <formula> <tex>${{V}_{rms}}$</tex> </formula> white supply noise, the ADPLL gives rms jitters of 8.7 and 0.63 ps at 8 GHz when the ACSC is disabled and enabled, respectively. The overall power consumption and the area of the presented ADPLL are 9.48 mW and 0.055 mm², respectively.N

A 32-Gb/s PAM4-Binary Bridge With Sampler Offset Cancellation for Memory Testing

This brief presents a 32-Gb/s PAM4-Binary bridge for the next-generation memory testing. The bridge incorporates all the required functions to evaluate a high-speed PAM4 memory using a low-speed NRZ tester. The low-speed data transmitted from the NRZ tester to the bridge are converted into high-speed PAM4 data through half-rate clock control and forwarded to the memory, and vice-versa. The ground-terminated PAM4 driver provides the single-ended output by controlling the output current with a 2-tap feed-forward equalizer, achieving a ratio level mismatch (RLM) of 0.95. To minimize the offset at the PAM4 receiver, the offset cancellation circuit with an offset of 2.76mV consisting of a CTLE and sampling latches is employed, and the horizontal margin of the received PAM4 signal is 50% for BER<10(-9). An all-digital PLL integrated in the bridge doubles the 4-GHz WCK used as forwarded clock for the graphic memory. The count-based PAM4 eye-opening monitor is also proposed to find the optimal codes for the maximum eye opening using the PRBS7 data sequence. The bridge fabricated in the 40-nm CMOS technology occupies an active area of 1.6mm(2) and dissipates 132mW.N