A 32-Gb/s PAM4-Binary Bridge With Sampler Offset Cancellation for Memory Testing

Abstract

This brief presents a 32-Gb/s PAM4-Binary bridge for the next-generation memory testing. The bridge incorporates all the required functions to evaluate a high-speed PAM4 memory using a low-speed NRZ tester. The low-speed data transmitted from the NRZ tester to the bridge are converted into high-speed PAM4 data through half-rate clock control and forwarded to the memory, and vice-versa. The ground-terminated PAM4 driver provides the single-ended output by controlling the output current with a 2-tap feed-forward equalizer, achieving a ratio level mismatch (RLM) of 0.95. To minimize the offset at the PAM4 receiver, the offset cancellation circuit with an offset of 2.76mV consisting of a CTLE and sampling latches is employed, and the horizontal margin of the received PAM4 signal is 50% for BER<10(-9). An all-digital PLL integrated in the bridge doubles the 4-GHz WCK used as forwarded clock for the graphic memory. The count-based PAM4 eye-opening monitor is also proposed to find the optimal codes for the maximum eye opening using the PRBS7 data sequence. The bridge fabricated in the 40-nm CMOS technology occupies an active area of 1.6mm(2) and dissipates 132mW.N