TCAD Simulation Models, Parameters, and Methodologies for β-Ga2O3 Power Devices

β-Ga2O3 is an emerging material and has the potential to revolutionize power electronics due to its ultra-wide-bandgap (UWBG) and lower native substrate cost compared to Silicon Carbide and Gallium Nitride. Since β-Ga2O3 technology is still not mature, experimental study of β-Ga2O3 is difficult and expensive. Technology-Computer-Aided Design (TCAD) is thus a cost-effective way to study the potentials and limitations of β-Ga2O3 devices. In this paper, TCAD parameters calibrated to experiments are presented. They are used to perform the simulations in heterojunction p-NiO/n-Ga2O3 diode, Schottky diode, and normally-off Ga2O3 vertical FinFET. Besides the current-voltage (I-V) simulations, breakdown, capacitance-voltage (C-V), and short-circuit ruggedness simulations with robust setups are discussed. TCAD Sentaurus is used in the simulations but the methodologies can be applied in other simulators easily. This paves the road to performing a holistic study of β-Ga2O3 devices using TCAD

Robust cryogenic ab-initio quantum transport simulation for L\u3csub\u3eG\u3c/sub\u3e = 10 nm nanowire

In this paper, we propose a simulation methodology for robust and accurate ab-initio quantum transport simulation down to 3 K of an n-type Si nanowire. This is important to understand the subthreshold swing (SS) at cryogenic temperature. We show that for LG = 10 nm, the SS is fully dominated by direct tunneling at cryogenic temperature, which is the first time to be demonstrated using ab-initio simulation, to the best of our knowledge. We propose a method to achieve more than 2x speed up in the simulation time and achieve convergence at high gate biases. It is also shown that from the leakage perspective, there is no advantage in operating LG = 10 nm transistor below 77 K

Advanced TCAD simulation and calibration of gallium oxide vertical transistor

In this paper, advanced β-Ga2O3 TCAD simulation parameters and methodologies are presented by calibrating simulation setup to vertical junctionless multi-gate transistor experimental data. Through careful calibration, several important β-Ga2O3 device physics are identified. The effects of compensation doping and incomplete ionization of dopants are investigated. Electron Philips unified carrier mobility (PhuMob) model, which can capture the temperature effect, is used. We also show that interfacial traps possibly play no role on the non-ideal sub-threshold slope (SS) and short channel effect is the major cause of SS degradation. The breakdown mechanism of the junctionless Ga2O3 transistor is also discussed and is shown to be limited by channel punch-through in off-state. The calibrated models match experimental Capacitance-Voltage (CV) and Current-Voltage (IV) well and can be used to predict the electrical performance of novel β-Ga2O3 devices

Study of Vertical Ga\u3csub\u3e2\u3c/sub\u3eO\u3csub\u3e3\u3c/sub\u3e FinFET Short Circuit Ruggedness using Robust TCAD Simulation

In this paper, the short circuit ruggedness of Gallium Oxide (Ga2O3) vertical FinFET is studied using Technology Computer-Aided-Design (TCAD) simulations. Ga2O3 is an emerging ultra-wide bandgap material and Ga2O3 vertical FinFET can achieve the normally-off operation for high voltage applications. Ga2O3 has a relatively low thermal conductivity and, thus, it is critical to explore the design space of Ga2O3 vertical FinFETs to achieve an acceptable short-circuit capability for power applications. In this study, appropriate TCAD models and parameters calibrated to experimental data are used. For the first time, the breakdown voltage simulation accuracy of Ga2O3 vertical FinFETs is studied systematically. It is found that a background carrier generation rate between 105 cm−3s−1 and 1012 cm−3s−1 is required in simulation to obtain correct results. The calibrated and robust setup is then used to study the short circuit withstand time (SCWT) of an 800 V-rated Ga2O3 vertical FinFET with different inter-fin architectures. It is found that, due to the high thermal resistance in Ga2O3, to achieve an SCWT \u3e1 μs, low gate overdrive is needed which increases Ron,sp by 66% and that Ga2O3 might melt before the occurrence of thermal runaway. These results provide important guidance for developing rugged Ga2O3 power transistors

Step-by-Step HHL Algorithm Walkthrough to Enhance the Understanding of Critical Quantum Computing Concepts

After learning basic quantum computing concepts, it is desirable to reinforce the learning using an important and relatively complex algorithm through which the students can observe and appreciate how the qubits evolve and interact with each other. Harrow-Hassidim-Lloyd (HHL) quantum algorithm, which can solve Linear System Problems with exponential speed-up over the classical method and is the basic of many important quantum computing algorithms, is used to serve this purpose. The HHL algorithm is explained analytically followed by a 4-qubit numerical example in bra-ket notation. Matlab code corresponding to the numerical example is available for students to gain a deeper understanding of the HHL algorithm from a pure matrix point of view. A quantum circuit programmed using qiskit is also provided which can be used for real hardware execution in IBM quantum computers. After going through the material, students are expected to have a better appreciation of the concepts such as basis transformation, bra-ket and matrix representations, superposition, entanglement, controlled operations, measurement, Quantum Fourier Transformation, Quantum Phase Estimation, and quantum programming. To help readers review these basic concepts, brief explanations augmented by the HHL numerical examples in the main text are provided in the Appendix

Energy Filtering Effect at Source Contact on Ultra-Scaled MOSFETs

We postulate that in ultra-scaled Field Effect Transistors (FET), such as nanowires in sub-7nm technology, the source contact will act as an energy filter and increase the effective temperature of carriers arriving at the channel barrier. This is due to the absence of inelastic scattering in the short source-contact-to-channel region. As a result, the Sub-threshold Slope (SS) will increase substantially. In this paper, we verify this energy filtering effect through numerical calculations and Technology Computer-Aided-Design (TCAD) simulations calibrated to quantum solvers for electrostatics. It is found that SS degradation increases as the source metal workfunction increases. At 300K, in the nanowire simulated, SS increases from 94mV/dec to 109mV/dec for gate length, LG, = 10 nm and from 72mV/dec to 88mV/dec for LG= 15 nm, representing an increase of effective carrier temperature from 300K to more than 340K. The simulation result is also verified by including the Schroedinger equation (SE) for tunneling in TCAD simulation. It is also found that such an effect is worse at higher device temperature and disappears at cryogenic temperature

A simulation methodology for superconducting qubit readout fidelity

Qubit readout is a critical part of any quantum computer including the superconducting-qubit-based one. The readout fidelity is affected by the readout pulse width, readout pulse energy, resonator design, qubit design, qubit-resonator coupling, and the noise generated along the readout path. It is thus important to model and predict the fidelity based on various design parameters along the readout path. In this work, a simulation methodology for superconducting qubit readout fidelity is proposed and implemented using Matlab and Ansys HFSS to allow co-optimization in the readout path. As an example, parameters are taken from an actual superconducting-qubit-based quantum computer. Without any calibrations, the model is able to predict the readout error of the system as a function of the readout pulse power. It is found that the system can still maintain high fidelity even if the input power is reduced by 7 dB. This can be used to guide the design and optimization of a superconducting qubit readout system

Vertical GaN diode BV maximization through rapid TCAD simulation and ML-enabled surrogate model

In this paper, two methodologies are used to speed up the maximization of the breakdown voltage (BV) of a vertical GaN diode that has a theoretical maximum BV of ∼ 2100 V. Firstly, we demonstrated a 5X faster accurate simulation method in Technology Computer-Aided-Design (TCAD). This allows us to find 50 % more numbers of high BV (\u3e1400 V) designs at a given simulation time. Secondly, a machine learning (ML) model is developed using TCAD-generated data and used as a surrogate model for differential evolution optimization. It can inversely design an out-of-the-training-range structure with BV as high as 1887 V (89 % of the ideal case) compared to ∼ 1100 V designed with human domain expertise

Vertical GaN Diode BV Maximization through Rapid TCAD Simulation and ML-enabled Surrogate Model

In this paper, two methodologies are used to speed up the maximization of the breakdown volt-age (BV) of a vertical GaN diode that has a theoretical maximum BV of ~2100V. Firstly, we demonstrated a 5X faster accurate simulation method in Technology Computer-Aided-Design (TCAD). This allows us to find 50% more numbers of high BV (>1400V) designs at a given simulation time. Secondly, a machine learning (ML) model is developed using TCAD-generated data and used as a surrogate model for differential evolution optimization. It can inversely design an out-of-the-training-range structure with BV as high as 1887V (89% of the ideal case) compared to ~1100V designed with human domain expertise.Comment: 4 pages, 7 figure

Improvement of TCAD Augmented Machine Learning Using Autoencoder for Semiconductor Variation Identification and Inverse Design

A machine learning (ML) model by combing two autoencoders and one linear regression model is proposed to avoid overfitting and to improve the accuracy of Technology Computer-Aided Design (TCAD)-augmented ML for semiconductor structural variation identification and inverse design, without using domain expertise. TCAD-augmented ML utilizes TCAD simulations to generate sufficient data for ML model development when experimental data are inadequate. The ML model can then be used to identify semiconductor structural variation for given experimental electrical measurements. In this study, the variation of layer thicknesses in the p-i-n diode is used as a demonstration. An ML model is developed to predict the diode layer thicknesses based on a given Current-Voltage (IV) curve. Although the variations of interest can be incorporated easily in TCAD simulations to generate ML training data, the TCAD-augmented ML model generally is overfitted and cannot predict the variations in experiment well due to hidden variables which also alters the IV curves. We show that by using an autoencoder, this problem can be solved. To verify the effectiveness, another set of TCAD simulation data is generated with hidden variables (dopant concentration variation) to emulate experimental data. Testing on the second set of data shows that the proposed model can avoid overfitting and has up to 15 times improvement in accuracy in thickness prediction. Moreover, this model is used successfully to perform inverse design and can capture an underlying physics that cannot be described by a simple physical parameter