Positive oxide-charge generation during 0.25 µm PMOSFET hot-carrier degradation

\u3cp\u3eA new hot-carrier degradation mechanism becomes important in 0.25 µm PMOSFET's. Hot-hole injection generates positive oxide charge near the drain. We determine the time dependence and the oxide-thickness dependence and we show a considerable enhancement of this degradation mechanism for nitrided gate oxides. For many bias conditions and many geometries, the time dependence of PMOSFET degradation can be successfully described by a summation of the time dependences of three separate degradation mechanisms: generation of interface states, negative oxide charge and positive oxide charge.\u3c/p\u3

Three hot-carrier degradation mechanisms in deep-submicron PMOSFET's

\u3cp\u3eHot-carrier degradation is mainly caused by negative oxide-charge generation in the present-day PMOS.FET's. We present experimental evidence showing that two more degradation mechanisms are important in the case of deep-submicron PMOSFET's. Firstly, the generation of interface states is significant in the case of sub-half-micron PMOSFET's. It even limits the lifetime of surface-channel transistors. Secondly, the generation of positive oxide charge by holes influences the characteristics. The latter process has been established unambiguously for the first time in PMOSFET's. We measured the bias dependence, the length dependence, and the time dependence separately for all three microscopic degradation mechanisms. We calculated the influence of these three mechanisms on the transconductance degradation. Summation of the three effects yields an excellent description of the experimentally determined time dependence of PMOSFET degradation for many bias conditions and various transistor geometries with either nitrided or conventional gate oxide.\u3c/p\u3

New hot-carrier degradation mechanisms in 0.25 μm PMOSFETs

\u3cp\u3ePMOSFET hot-carrier reliability is often proposed to be limited by negative oxide charge. We show that interface states determine the lifetime in deep submicron PMOSFETs. Clear evidence for additional positive oxide-charge generation is presented for the first time. The bias-length- and time dependences are measured for all three degradation mechanisms. Combining these three mechanism describes the time dependence of PMOSFET degradation convincingly for many geometries at many bias conditions.\u3c/p\u3

N\u3csub\u3e2\u3c/sub\u3eO nitrided gate dielectric technology for 0.25 μm CMOS

\u3cp\u3eA technology for thin N\u3csub\u3e2\u3c/sub\u3eO nitrided gate oxide was developed for 0.25 μm CMOS. A gate dielectric of 7.5 nm thickness was grown using a two-step furnace process. The first step is oxidation in diluted dry oxygen at 900° C, the second step is nitridation in pure N\u3csub\u3e2\u3c/sub\u3eO at 950° C. The use of lightly nitrided gate dielectrics improved the gate oxide quality and did not degrade the MOS device properties. Furthermore boron diffusion through the thin dielectric of BF\u3csub\u3e2\u3c/sub\u3e doped poly gates was suppressed by N\u3csub\u3e2\u3c/sub\u3eO nitridation.\u3c/p\u3

A low power 0.25 μm CMOS technology

\u3cp\u3eA 0.25 μ m CMOS technology with scaled LOCOS isolation, twin implanted well, 7.5 nm gate oxide thickness, surface channel NMOS and PMOS devices, shallow n- and p-junctions and thin TiSi\u3csub\u3e2\u3c/sub\u3e salicide is described. The technology is optimized for a reduced supply voltage of 2.5 V. The device design and fabrication, device characterisation and inverter delay are presented.\u3c/p\u3

Lightly N\u3csub\u3e2\u3c/sub\u3eO nitrided dielectrics grown in a conventional furnace for E\u3csup\u3e2\u3c/sup\u3ePROM and 0.25 μm CMOS

\u3cp\u3eFor deep-submicron CMOS transistors and FLOTOX E\u3csup\u3e2\u3c/sup\u3ePROM devices a considerable improvement in reliability and performance can be achieved when nitrided dielectrics are used. We developed an N\u3csub\u3e2\u3c/sub\u3eO nitridation technology for a conventional furnace. Oxidation and nitridation are done in one run with a two-step and low-thermal budget processing to grow a dielectric layer with a thickness of 6-10 nm.\u3c/p\u3

The impact of scaling on hot-carrier degradation and supply voltage of deep-submicron NMOS transistors

\u3cp\u3eAn experimental study of hot carrier degradation and power supply voltage scaling of deep-submicron NMOS devices is presented. Devices were optimized for processes with design rule between 2 μ m and 0.17 μ m. Charge pumping measurements showed that the lifetime based on interface state generation in the devices was determined only by I\u3csub\u3esub\u3c/sub\u3e/I\u3csub\u3ed\u3c/sub\u3e and the drain current. It did not depend on gate length, oxide thickness, and substrate doping. The lifetime (determined by shifts in the maximum linear transconductance) of the devices with minimum gate length of different processes fall on a single life in plots of tau I\u3csub\u3ed\u3c/sub\u3e versus I\u3csub\u3esub\u3c/sub\u3e/I\u3csub\u3ed\u3c/sub\u3e. This behavior can be explained by the impact of interface damage on the transistor parameters of these devices. Light emission spectra and device simulation showed that nonlocal carrier heating becomes important for devices from deep-submicron processes. As a result the power supply voltage is almost independent of design rule for the deep-submicron process (V\u3csub\u3edd\u3c/sub\u3e<or=2.5 V).\u3c/p\u3