Low-Pressure CVD of Germanium-Silicon films using Silane and Germane sources

In this work a study of Low Pressure Chemical Vapour Deposition (LPCVD) of Germanium-Silicon films has been carried out. The films were deposited on thermally oxidised silicon wafers using a horizontal hot-wall LPCVD system, at deposition temperatures ranging from 430 to 480 oC and total pressures from 3 to 200 Pa. Pure GeH4 and SiH4 gas sources were used for the experiments. Growth kinetics and texture of GexSi1-x films versus varying deposition conditions, resulting in different film properties, were investigated. The effect of Germanium content in the layers on deposition rate at 430 oC and the change in the film crystallinity caused by deposition at different deposition pressures were studied

Breakdown and recovery of thin gate oxides

Breakdown events are studied in varying test set-ups with a high time resolution. Often a partial recovery from breakdown is observed\ud within a few ms. Parameters such as device area, stress conditions and parasitic elements prohibit the recovery if they result in a high system impedance. The results suggest the existence of a highly conductive path that can be annihilated during breakdown

W-CMP for sub-micron inverse metallisation

Chemical Mechanical Polishing (CMP) of tungsten for an inverse metallisation scheme is investigated. The influence of CMP parameters on removal rate and uniformity is studied. The main effects on the removal rate are the applied pressure and the rotation rate of the polishing pad. To the first order Preston's equation is obeyed. The uniformity is best with equal rpm of pad and wafer and with perforated pads. Also, pattern density effects of CMP of W/PETEOS are investigated. Dishing increased at larger W-linewidth. Oxide erosion increased at larger pattern density and smaller W-linewidth. Electrical measurements on submicron (0.4 and 0.5 ¿m) test structures yielded good CMP results

High-Performance Deep SubMicron CMOS Technologies with Polycrystalline-SiGe Gates

The use of polycrystalline SiGe as the gate material for deep submicron CMOS has been investigated. A complete compatibility to standard CMOS processing is demonstrated when polycrystalline Si is substituted with SiGe (for Ge fractions below 0.5) to form the gate electrode of the transistors. Performance improvements are achieved for PMOS transistors by careful optimization of both transistor channel profile and p-type gate workfunction, the latter by changing Ge mole fraction in the gate. For the 0.18 ¿m CMOS generation we record up to 20% increase in the current drive, a 10% increase in the channel transconductance and subthreshold swing improvement from 82 mV/dec to 75 mV/dec resulting in excellent ¿on¿/¿off¿ currents ratio. At the same time, NMOS transistor performance is not affected by gate material substitutio

Modelling of dishing for metal chemical mechanical polishing

In this paper, a physical model for the development of dishing during metal chemical mechanical polishing (CMP) is proposed. The main assumption of the model is that material removal occurs predominantly at the pad/wafer contacts. The distribution of pad/wafer contact size is studied first. This distribution is used as an input for a model of the dependence for the material removal rate on the line width. A relation that describes the development of dishing as a function of overpolish time will be presented. The model describes to a great accuracy the observed dishing effects, using one free paramete

Thin SIMOX SOI material for half-micron CMOS

\u3cp\u3eThe properties of half-micron CMOS devices fabricated on thin film SIMOX SOI with different material quality will be presented. The gate oxide quality, diode leakage current and breakdown voltage of transistors will be shown. The influence of LDD dope and TiSi\u3csub\u3e2\u3c/sub\u3esalicide on the parasitic bipolar transistor breakdown is presented. Temperature measurements on SOI and bulk transistors are presented which show an increased heating effect for thin film SOI transistors.\u3c/p\u3

An experimental investigation on weak localisation, spin-orbit and interaction effects in thin bismuth films

\u3cp\u3eThe authors have measured the low-temperature (0.02<T<10K) electronic conductivity, magnetoresistance and Hall constant in thin (20-200 nm) bismuth films. The aim was to study weak localisation, spin-orbit and electron-electron interaction mechanisms in this well suited material. The authors compared their data with theories of Hikami et al. (1980) and Altshuler et al. (1980, 1981). It was found that their data must be interpreted in terms of two independent mechanisms, i.e. electron-electron interaction and spin-orbit scattering. Weak localisation is completely suppressed by the strong spin-orbit scattering in this material.\u3c/p\u3

Comparison of buried and surface channel PMOS devices for low voltage 0.5 μm CMOS

\u3cp\u3eA low voltage option in a 0.5 μm CMOS process technology is described. The key technological issue is the threshold voltage and sub-threshold leakage characteristics of the PMOS devices. The device properties of the n\u3csup\u3e+\u3c/sup\u3e-gate buried channel devices will be compared with the corresponding p\u3csup\u3e+\u3c/sup\u3e-gate surface channel devices. For power supply voltages down to 0.9 V the surface channel PMOS devices revealed superior transistor performance. Furthermore, the off-current characteristics are superior to the n\u3csup\u3e+\u3c/sup\u3e-gate buried channel devices. A minimum threshold voltage of -0.35 V of the 0.45 μm physical gate length PMOS transistor with less then 0.1 nA/μm leakage current was realised in a 0.5 μm CMOS process.\u3c/p\u3

A simple model for quantisation effects in heavily-doped silicon MOSFETs at inversion conditions

\u3cp\u3eThe transistor parameters of state-of-the-art MOSFETs are affected by quantisation effects of the carrier motion in the inversion channel. To account for these effects in classical device stimulators, we show that a better modeling of the silicon bandgap at inversion conditions is ifE\u3csub\u3eg\u3c/sub\u3e\u3csup\u3eQM\u3c/sup\u3e = E\u3csub\u3eg\u3c/sub\u3e\u3csup\u3eCONV\u3c/sup\u3e + 13 9Δε{lunate} in which Δε{lunate} is the position of the first energy level with respect to the bottom of the conduction band. The improved modeling of the bandgap leads to a new model for the intrinsic carrier concentration n\u3csub\u3ei\u3c/sub\u3e. The model for n\u3csub\u3ei\u3c/sub\u3e has been tested against measurements and against self-consistent QM calculations. Excellent agreement is obtained.\u3c/p\u3