Heterogeneous Integration and Fabrication of III-V MOS Devices in a 200mm Processing Environment

We report on the fabrication of MOS capacitors on 200 mm virtual GaAs substrates using a Si CMOS processing environment. The fabricated capacitors were comparable to those processed on bulk GaAs material. Topside contact was made to the GaAs using a novel CMOS compatible self-aligned NiGe contact scheme resulting in a measured contact resistance of 0.26 [ohm sign].cm. Cross-contamination from various III-V substrates was investigated and it was found that by limiting the thermal budget to <= 300C cross-contamination from the outgassing of In, Ga and As could be eliminated. For wet processing the judicious choice of recipe and processing conditions resulted in no significant cross-contamination being detected as determined by TXRF monitoring. This achievement enables III-V device production using state-of-the-art Si processing equipment.Peer reviewe

A 400GHz fMAX Fully Self-Aligned SiGe:C HBT Architecture

peer reviewedAn improved fully self-aligned SiGe:C HBT architecture featuring a single-step epitaxial collector-base process is described. An fMAX value of 400 GHz is reached by structural as well as intrinsic advancements made to the HBT device

Integration of InGaAs Channel n-MOS Devices on 200mm Si Wafers Using the Aspect-Ratio-Trapping Technique

peer reviewedWe report on the fabrication on InGaAs/InP implant free quantum well (IFQW) n-MOSFET devices on 200mm wafers in a Si CMOS processing environment. The starting virtual InP substrates were prepared by means of the aspect-ratio-trapping technique. Post CMP these substrate resulted in a planar substrate with a rms roughness of 0.32 nm. After channel and gate processing source drain regions were formed by the selective epitaxial growth of Si doped InGaAs. Contact to the source/drain regions was made by a standard W-plug/metal 1 process. The contact resistance was estimated to be on the order of 7x10-7 [ohm sign].cm2. Fully processed devices clearly showed gate modulation albeit on top of high levels of source to drain leakage. The source of this leakage was determined to be the result of the unintentional background doping of the InP buffer layer. Simulations show that the inclusion of the p-InAlAs between the InP and InGaAs can effectively suppress this leakage. This work is a significant step towards the integration of InGaAs based devices on a standard CMOS platform

Integration of InGaAs Channel n-MOS Devices on 200mm Si Wafers Using the Aspect-Ratio-Trapping Technique

peer reviewe

Ge deep sub-micron HiK/MG pFETs with superior drive compared to Si HiK/MG state-of-the-art reference

This work presents HiK/metal gate Ge MOSFET devices with a conventional layout and made in a complete Si-like process flow. The fabricated pFET long-channel conventional devices equal the best pFET long-channel mobility results obtained elsewhere on ring-shaped devices made with simplified process flows. The hole mobility is significantly above the Si universal, with a peak mobility value of ∼250 cm² (V s)⁻¹. The fabricated nFET devices have electron mobility much lower than the Si universal, as is commonly observed. Also, deep sub-micron Ge pFET devices with gate lengths below 0.2 μm have been made. The implementation of a novel NiSi-like NiGe module is key to obtain deep sub-micron devices with not only a high-mobility channel, but also with an acceptably low series resistance. 0.19 μm deep sub-micron Ge devices with germanided source/drain regions demonstrate that the mobility enhancement observed in long-channel Ge pFETs as compared to Si HiK/metal gate pFETs can indeed result in deep sub-micron Ge devices with a higher drive.status: publishe

Selective epitaxial growth of III-V semiconductor heterostructures on Si substrates for logic applications

peer reviewedWe have deposited III-V alloys on 200 mm Si miscut wafers with an oxide pattern. The selective epitaxial growth (SEG) of GaAs in large windows defined by SiO2 lines on a thick strained-relaxed Ge buffer layer served as a test vehicle which allowed us to demonstrate the integration of a III-V material deposition process step in a Si manufacturing line using an industrial reactor. High quality GaAs layers with high wafer-scale thickness uniformity were achieved. In a subsequent step, SEG of InP was successfully performed on wafers with a 300 nm shallow trench isolation pattern. The seed layer morphology depended on the treatment of the Ge surface and on the growth temperature. The orientation of the trench with respect to the substrate miscut direction had an impact on the quality of the InP filling. Despite of the challenges, such an approach for the integration of III-V materials on Si substrates allowed us to obtain extended-defect-free epitaxial regions suitable for the fabrication of high-performance devices

High hole mobility in 65 nm strained Ge p-Channel field effect transistors with HfO2Gate dielectric

Biaxially-strained Ge p-channel field effect transistors (pFETs) have been fabricated for the first time in a 65 nm technology. The devices are designed to have a reduced effective oxide thickness (EOT) while maintaining minimized short channel effects. Low and high field transport has been studied by in-depth electrical characterization, showing a high hole-mobility that is enhanced by up to 70% in the strained devices. The important role of pocket implants in degrading the drive current is highlighted. Using a judicious implantation scheme, we demonstrate a significant gain in on-current (up to 35%) for nanoscaled strained Ge pFETs. Simultaneous optimization of the gate metal and dielectric, together with the corresponding uniaxial stress engineering, is identified as a promising path for further performance enhancement