A high-energy ion implanted BICMOS process with compatible EPROM structures

A 1.5µm high-energy ion implanted BiCMOS process is proposed. This process offers NMOS, PMOS, vertical npn transistors and VIPMOS-EPROM devices. The process structure is modular in order to achieve CMOS and bipolar transistors in uncompromised forms. Consequently, the N-well and collector regions are defined separately. Conflicting requirements for the collector doping profile have been optimized towards practical electrical device characteristics

Improvement of device characteristics by multiple step implants or introducing a C gettering layer

Ion implantation is used for realization of the collector in vertical bipolar transistors in a BiCMOS process. Secondary defects, remaining after annealing the implant damage, can give rise to an increased leakage current and to collector-emitter shorts. Two methods are proposed to avoid dislocation formation. First, by using multiple step implants, and second, by application of a carbon gettering layer. Experimental results show that these schemes can lower leakage currents, and moreover dramatically increase device yield. However, the carbon profile needs a further optimization with respect to the quality of the collector-substrate junction

Modeling of VIPMOS hot electron gate currents

A buried injector, which is biased by means of punch-through, can be used in substrate hot electron injection EEPROM devices [1]. In order to optimize this device an empirical expression for the injection probability as a function of the effective barrier height and the average electron energy is proposed and verified by measurements on a variety of devices