Quantum Electroweak Symmetry Breaking Through Loop Quadratic Contributions

Based on two postulations that (i) the Higgs boson has a large bare mass $m_H \gg m_h \simeq 125$ GeV at the characteristic energy scale $M_c$ which defines the standard model (SM) in the ultraviolet region, and (ii) quadratic contributions of Feynman loop diagrams in quantum field theories are physically meaningful, we show that the SM electroweak symmetry breaking is induced by the quadratic contributions from loop effects. As the quadratic running of Higgs mass parameter leads to an additive renormalization, which distinguishes from the logarithmic running with a multiplicative renormalization, the symmetry breaking occurs once the sliding energy scale $\mu$ moves from $M_c$ down to a transition scale $\mu =\Lambda_{EW}$ at which the additive renormalized Higgs mass parameter $m^2_H(M_c/\mu)$ gets to change the sign. With the input of current experimental data, this symmetry breaking energy scale is found to be $\Lambda_{EW}\simeq 760$ GeV, which provides another basic energy scale for the SM besides $M_c$. Studying such a symmetry breaking mechanism could play an important role in understanding both the hierarchy problem and naturalness problem. It also provides a possible way to explore the experimental implications of the quadratic contributions as $\Lambda_{EW}$ lies within the probing reach of the LHC and the future Great Collider.Comment: 10 pages, 2 figures, published versio

Performance Evaluation and Modeling of HPC I/O on Non-Volatile Memory

HPC applications pose high demands on I/O performance and storage capability. The emerging non-volatile memory (NVM) techniques offer low-latency, high bandwidth, and persistence for HPC applications. However, the existing I/O stack are designed and optimized based on an assumption of disk-based storage. To effectively use NVM, we must re-examine the existing high performance computing (HPC) I/O sub-system to properly integrate NVM into it. Using NVM as a fast storage, the previous assumption on the inferior performance of storage (e.g., hard drive) is not valid any more. The performance problem caused by slow storage may be mitigated; the existing mechanisms to narrow the performance gap between storage and CPU may be unnecessary and result in large overhead. Thus fully understanding the impact of introducing NVM into the HPC software stack demands a thorough performance study. In this paper, we analyze and model the performance of I/O intensive HPC applications with NVM as a block device. We study the performance from three perspectives: (1) the impact of NVM on the performance of traditional page cache; (2) a performance comparison between MPI individual I/O and POSIX I/O; and (3) the impact of NVM on the performance of collective I/O. We reveal the diminishing effects of page cache, minor performance difference between MPI individual I/O and POSIX I/O, and performance disadvantage of collective I/O on NVM due to unnecessary data shuffling. We also model the performance of MPI collective I/O and study the complex interaction between data shuffling, storage performance, and I/O access patterns.Comment: 10 page