To Sense or to Transmit: A Learning-Based Spectrum Management Scheme for Cognitive Radiomesh Networks

Abstract—Wireless mesh networks, composed of interconnected clusters of mesh router (MR) and multiple associated mesh clients (MCs), may use cognitive radio equipped transceivers, allowing them to choose licensed frequencies for high bandwidth communication. However, the protection of the licensed users in these bands is a key constraint. In this paper, we propose a reinforcement learning based approach that allows each mesh cluster to independently decide the operative channel, the durations for spectrum sensing, the time of switching, and the duration for which the data transmission happens. The contributions made in this paper are threefold. First, based on accumulated rewards for a channel mapped to the link transmission delays, and the estimated licensed user activity, the MRs assign a weight to each of the channels, thereby selecting the channel with highest performance for MCs operations. Second, our algorithm allows dynamic selection of the sensing time interval that optimizes the link throughput. Third, by cooperative sharing, we allow the MRs to share their channel table information, thus allowing a more accurate learning model. Simulations results reveal significant improvement over classical schemes which have pre-set sensing and transmission durations in the absence of learning. I

Optimal instruction scheduling and register allocation for multiple-issue processors.

As processors make use of wider instruction issue and deeper pipelines, the number of instructions in flight and consequently the number of simultaneously live values per cycle increases. Fine grain scheduling and register allocation algorithms need to be closely coupled to make the best use of the available parallelism. In my research, I have developed a group of optimal scheduling and register allocation algorithms for statically scheduled processors that can issue more than one operation per cycle. This class of processors includes vector supercomputers and VLIW computers such as the Cydra-5 and Multiflow Trace VLIW computers and the Kendall Square Research (KSR) machine. My contributions include: An integer linear programming formulation that computes the shortest schedule for a general multiple-issue processor. This formulation inserts spills where needed, puts no restrictions on the program dependence graph, and admits a wide range of processors with specifiable issue widths, instruction latencies, and register set size. A quadratic time algorithm that optimally schedules a binary dependence tree on a dual-issue processor under the classical restriction that the operations all have unit latency. By showing that at least one optimal solution is in contiguous form and that all k-spill contiguous form schedules have the same cost, I am able to eliminate all but one k-spill candidate schedule from consideration. A dynamic programming algorithm to find an optimal register allocation that minimizes spill cost for a given, dual-issue, instruction schedule. Value exclusions and implicit and explicit pruning rules are used to substantially reduce the size of the search space.Ph.D.Computer Science and EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/105122/1/9635568.pdfDescription of 9635568.pdf : Restricted to UM users only

Optimal Local Register Allocation for a Multiple-Issue Machine

This paper presents an algorithm that allocates registers optimally for straight-line code running on a generic multi-issue computer. On such a machine, an optimal register allocation is one that minimizes the number of issue slots that the code requires. Optimal spill selection and load/store placement are used to minimize the number of additional issue slots needed, given a schedule for the non-memory reference instructions and a fixed number of available physical registers. The generic multi-issue machine model closely models the operation of vector and VLIW processors, and could be extended to model super-scalar processors. The algorithm uses dynamic programming to search the state space of plausible register allocations; implicit and explicit state pruning are used to make the problem tractable. The optimal allocation produced by the algorithm for a substantial example is presented. 1 Introduction High performance processors are increasingly memory bottlenecked due to increasin..

An Adjustable Linear Time Parallel Algorithm for Maximum Weight Bipartite Matching Information Processing Letters

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