Low-Frequency Noise in Layered ReS₂ Field Effect Transistors on HfO₂ and Its Application for pH Sensing

Layered rhenium disulfide (ReS₂) field effect transistors (FETs), with thickness ranging from few to dozens of layers, are demonstrated on 20 nm thick HfO₂/Si substrates. A small threshold voltage of −0.25 V, high on/off current ratio of up to ∼10⁷, small subthreshold swing of 116 mV/dec, and electron carrier mobility of 6.02 cm²/V·s are obtained for the two-layer ReS₂ FETs. Low-frequency noise characteristics in ReS₂ FETs are analyzed for the first time, and it is found that the carrier number fluctuation mechanism well describes the flicker (1/<i>f</i>) noise of ReS₂ FETs with different thicknesses. pH sensing using a two-layer ReS₂ FET with HfO₂ as a sensing oxide is then demonstrated with a voltage sensitivity of 54.8 mV/pH and a current sensitivity of 126. The noise characteristics of the ReS₂ FET-based pH sensors are also examined, and a corresponding detection limit of 0.0132 pH is obtained. Our studies suggest the high potential of ReS₂ for future low-power nanoelectronics and biosensor applications

Detrimental Effects of Oxygen Vacancies in Electrochromic Molybdenum Oxide

Using the small polaron model, we show clearly that oxygen vacancy defects are detrimental to the electrochromic responses of molybdenum oxide (MoO₃). The observed phenomenon is explained by studying the oxidation states of the molybdenum (Mo) metal, which is central to the site specific small polaron model. First, we used the small polaron pair to explain the red-shift between the absorption peak induced by the vacancy defects and the inserted lithium (Li). Next, we show that any Mo⁵⁺ defects results in either a poor cathodic optical pair, or forms a site that is inactive for Li insertion. The main reason for the latter is due to the inability to generate Mo⁴⁺ in the reported optimal potential range. Finally, if the oxide starts with any intrinsic Mo⁴⁺ defect, we provided evidence to show that Mo⁶⁺–Mo⁴⁺ remains the only possible site for Li insertion, thereby greatly reducing available active sites. This optical modulation from Li insertion into this aforementioned pair is also low when compared with the Mo⁶⁺–Mo⁶⁺ pair. We therefore conclude that the most effective modulation is achieved by the Mo⁶⁺–Mo⁶⁺ pair and defects creation will be detrimental to the electrochromic performance of MoO₃

Damage-Free Smooth-Sidewall InGaAs Nanopillar Array by Metal-Assisted Chemical Etching

Producing densely packed high aspect ratio In_0.53Ga_0.47As nanostructures without surface damage is critical for beyond Si-CMOS nanoelectronic and optoelectronic devices. However, conventional dry etching methods are known to produce irreversible damage to III−V compound semiconductors because of the inherent high-energy ion-driven process. In this work, we demonstrate the realization of ordered, uniform, array-based In_0.53Ga_0.47As pillars with diameters as small as 200 nm using the damage-free metal-assisted chemical etching (MacEtch) technology combined with the post-MacEtch digital etching smoothing. The etching mechanism of In<i>_x</i>Ga_1−<i>x</i>As is explored through the characterization of pillar morphology and porosity as a function of etching condition and indium composition. The etching behavior of In_0.53Ga_0.47As, in contrast to higher bandgap semiconductors (<i>e</i>.<i>g</i>., Si or GaAs), can be interpreted by a Schottky barrier height model that dictates the etching mechanism constantly in the mass transport limited regime because of the low barrier height. A broader impact of this work relates to the complete elimination of surface roughness or porosity related defects, which can be prevalent byproducts of MacEtch, by post-MacEtch digital etching. Side-by-side comparison of the midgap interface state density and flat-band capacitance hysteresis of both the unprocessed planar and MacEtched pillar In_0.53Ga_0.47As metal-oxide-semiconductor capacitors further confirms that the surface of the resultant pillars is as smooth and defect-free as before etching. MacEtch combined with digital etching offers a simple, room-temperature, and low-cost method for the formation of high-quality In_0.53Ga_0.47As nanostructures that will potentially enable large-volume production of In_0.53Ga_0.47As-based devices including three-dimensional transistors and high-efficiency infrared photodetectors

Minimizing Isolate Catalyst Motion in Metal-Assisted Chemical Etching for Deep Trenching of Silicon Nanohole Array

The instability of isolate catalysts during metal-assisted chemical etching is a major hindrance to achieve high aspect ratio structures in the vertical and directional etching of silicon (Si). In this work, we discussed and showed how isolate catalyst motion can be influenced and controlled by the semiconductor doping type and the oxidant concentration ratio. We propose that the triggering event in deviating isolate catalyst motion is brought about by unequal etch rates across the isolate catalyst. This triggering event is indirectly affected by the oxidant concentration ratio through the etching rates. While the triggering events are stochastic, the doping concentration of silicon offers a good control in minimizing isolate catalyst motion. The doping concentration affects the porosity at the etching front, and this directly affects the van der Waals (vdWs) forces between the metal catalyst and Si during etching. A reduction in the vdWs forces resulted in a lower bending torque that can prevent the straying of the isolate catalyst from its directional etching, in the event of unequal etch rates. The key understandings in isolate catalyst motion derived from this work allowed us to demonstrate the fabrication of large area and uniformly ordered sub-500 nm nanoholes array with an unprecedented high aspect ratio of ∼12

Self-Anchored Catalyst Interface Enables Ordered Via Array Formation from Submicrometer to Millimeter Scale for Polycrystalline and Single-Crystalline Silicon

Defying text definitions of wet etching, metal-assisted chemical etching (MacEtch), a solution-based, damage-free semiconductor etching method, is directional, where the metal catalyst film sinks with the semiconductor etching front, producing 3D semiconductor structures that are complementary to the metal catalyst film pattern. The same recipe that works perfectly to produce ordered array of nanostructures for single-crystalline Si (c-Si) fails completely when applied to polycrystalline Si (poly-Si) with the same doping type and level. Another long-standing challenge for MacEtch is the difficulty of uniformly etching across feature sizes larger than a few micrometers because of the nature of lateral etching. The issue of interface control between the catalyst and the semiconductor in both lateral and vertical directions over time and over distance needs to be systematically addressed. Here, we present a self-anchored catalyst (SAC) MacEtch method, where a nanoporous catalyst film is used to produce nanowires through the pinholes, which in turn physically anchor the catalyst film from detouring as it descends. The systematic vertical etch rate study as a function of porous catalyst diameter from 200 to 900 nm shows that the SAC-MacEtch not only confines the etching direction but also enhances the etch rate due to the increased liquid access path, significantly delaying the onset of the mass-transport-limited critical diameter compared to nonporous catalyst c-Si counterpart. With this enhanced mass transport approach, vias on multistacks of poly-Si/SiO₂ are also formed with excellent vertical registry through the polystack, even though they are separated by SiO₂ which is readily removed by HF alone with no anisotropy. In addition, 320 μm square through-Si-via (TSV) arrays in 550 μm thick c-Si are realized. The ability of SAC-MacEtch to etch through poly/oxide/poly stack as well as more than half millimeter thick silicon with excellent site specificity for a wide range of feature sizes has significant implications for 2.5D/3D photonic and electronic device applications