DEFECTS FOR RANDOM TELEGRAPH NOISE AND NEGATIVE BIAS TEMPERATURE INSTABILITY

Random Telegraphy Noise (RTN) and Negative Bias Temperature Instability (NBTI) are two important sources of device instability. Their relation is not fully understood and is investigated in this work. We examine the similarity and differences of the defects responsible for them. By following the As-grown-Generation (AG) model proposed by our group, we present clear evidences that the As-grown hole traps (AHTs) are responsible for the RTN of pMOSFETs. AHTs also dominate NBTI initially, but the generated defects (GDs) become increasingly important for NBTI as stress time increases. The GDs, however, do not cause RTN

NBTI prediction and its induced time dependent variation

Negative bias temperature instability (NBTI) prediction relies on a reliable extraction of power exponents from its kinetics. When measured by fast pulse technique, however, the kinetics does not follow a power law. This paper reviews the recent progresses on how to restore the power law, based on the As-grown-Generation (AG) model. For nanometer sized devices, NBTI is different for different devices, inducing a time-dependent variation. The new technique proposed for characterizing this Time-dependent Variation accounting for within-a-device-Fluctuation (TVF) will be reviewed

Hot carrier aging of nano-scale devices: characterization method, statistical variation, and their impact on use voltage

Hot carrier aging (HCA) has attracted a lot of attentions recently, as it can be a lifetime limiting mechanism for both I/O and core devices. The applicability of the conventional characterization method developed for large devices to nano-scale devices is questionable, as nano-scale devices suffers from within-a-device-fluctuation (WDF). This work shows that the inclusion of WDF measured by the commercial quasi-DC SMU gives erroneous results. A method is proposed to separate the WDF from the real HCA for reliable parameter extraction of the HCA model. The lifetime and use voltage become yield dependent and the impact of statistical variations on SRAM is assessed

Assessing the Accuracy of Statistical Properties Extracted from a Limited Number of Device Under Test for Time Dependent Variations

As device sizes scale down, device variations scale up. There are two types of device-to-device variations (DDV): as-fabricated or time-zero DDV and the time dependent variations (TDV). Even if two nano-scaled devices were identical at time-zero, they would be different after stresses and result in TDV, since the defect generation and charging-discharging are stochastic. To characterize TDV, statistical properties, such as the mean value and standard deviation, are extracted from tests. Their accuracy improves as the number of device under tests (DUTs) increases. Ageing is time consuming and the typical DUTs used are in the range of tens to hundreds. There is little information on the accuracy of the statistical properties extracted from such a limited DUTs and the objective of this paper is to propose a methodology to assess it. Based on the defect-centric model, the accuracy with a specific confidence level is evaluated for a given number of DUTs and a stress level

Key issues and solutions for characterizing hot carrier aging of nano-meter scale nMOSFETs

Silicon bandgap limits the reduction of operation voltage when downscaling device sizes. This increases the electrical field within a device and hot carrier aging (HCA) is becoming an important reliability issue again for some CMOS technologies. For nano-devices, there are a number of challenges for characterizing their HCA: the random charge-discharge of traps in gate dielectric causes ‘within-a-device-fluctuation (WDF)’, making the parameter shift uncertain after a given HCA. This can introduce errors when extracting HCA time exponents and it will be shown that the lower envelope of the WDF must be used. Nano-devices also have substantial device-to-device variation (DDV) and multiple tests are needed for evaluating their standard deviation, σ, and mean value, µ. Repeating the time-consuming HCA tests is costly and a voltage-step-stress method is applied to reduce the number of tests by 80%. For a given number of devices under tests (DUTs), there is little information on the accuracy of the extracted σ and µ. We will develop a method to provide this information, based on the defect-centric model. For 40 DUTs with an average of 10 traps per device, the extracted µ and σ has an accuracy of ±14% and ±24% respectively with a 95% confidence

Development of a Technique for Characterizing Bias Temperature Instability-Induced Device-to-Device Variation at SRAM-Relevant Conditions

SRAM is vulnerable to device-to-device variation (DDV), since it uses minimum-sized devices and requires device matching. In addition to the as-fabricated DDV at time-zero, aging induces a time-dependent DDV (TDDV). Bias temperature instability (BTI) is a dominant aging process. A number of techniques have been developed to characterize the BTI, including the conventional pulse-(I) -(V) , random telegraph noises, time-dependent defect spectroscopy, and TDDV accounting for the within-device fluctuation. These techniques, however, cannot be directly applied to SRAM, because their test conditions do not comply with typical SRAM operation. The central objective of this paper is to develop a technique suitable for characterizing both the negative BTI (NBTI) and positive BTI (PBTI) in SRAM. The key issues addressed include the SRAM relevant sensing Vg, measurement delay, capturing the upper envelope of degradation, sampling rate, and measurement time window. The differences between NBTI and PBTI are highlighted. The impact of NBTI and PBTI on the cell-level performance is assessed by simulation, based on experimental results obtained from individual devices. The simulation results show that, for a given static noise margin, test conditions have a significant effect on the minimum operation bias

Insight into Electron Traps and Their Energy Distribution under Positive Bias Temperature Stress and Hot Carrier Aging

The access transistor of SRAM can suffer both Positive Bias Temperature Instability (PBTI) and Hot Carrier Aging (HCA) during operation. The understanding of electron traps (ETs) is still incomplete and there is little information on their similarity and differences under these two stress modes. The key objective of this paper is to investigate ETs in terms of energy distribution, charging and discharging properties, and generation. We found that both PBTI and HCA can charge ETs which center at 1.4eV below conduction band (Ec) of high-k (HK) dielectric, agreeing with theoretical calculation. For the first time, clear evidences are presented that HCA generates new ETs, which do not exist when stressed by PBTI. When charged, the generated ETs’ peak is 0.2eV deeper than that of pre-existing ETs. In contrast with the power law kinetics for charging the pre-existing ETs, filling the generated ETs saturates in seconds, even under an operation bias of 0.9 V. ET generation shortens device lifetime and must be included in modelling HCA. A cyclic and anti-neutralization ETs model (CAM) is proposed to explain PBTI and HCA degradation, which consists of pre-existing cyclic electron traps (PCET), generated cyclic electron traps (GCET), and anti-neutralization electron traps (ANET)

Impact of Hot Carrier Aging on Random Telegraph Noise and Within a Device Fluctuation

For nanometer MOSFETs, charging and discharging a single trap induces random telegraph noise (RTN). When there are more than a few traps, RTN signal becomes complex and appears as within a device fluctuation (WDF). RTN/WDF causes jitters in switch timing and is a major challenge to low power circuits. In addition to RTN/WDF, devices also age. The interaction between RTN/WDF and aging is of importance and not fully understood. Some researchers reported aging increasing RTN/WDF, while others showed RTN/WDF being hardly affected by aging. The objective of this work is to investigate the impact of hot carrier aging (HCA) on the RTN/WDF of nMOSFETs. For devices of average RTN/WDF, it is found that the effect of HCA is generally modest. For devices of abnormally high RTN/WDF, however, for the first time, we report HCA reducing RTN/WDF substantially (>50%). This reduction originates from either a change of current distribution or defect losses

Impact of Hot Carrier Aging on Random Telegraph Noise and Within a Device Fluctuation

For nanometer MOSFETs, charging and discharging a single trap induces random telegraph noise (RTN). When there are more than a few traps, RTN signal becomes complex and appears as within a device fluctuation (WDF). RTN/WDF causes jitters in switch timing and is a major challenge to low power circuits. In addition to RTN/WDF, devices also age. The interaction between RTN/WDF and aging is of importance and not fully understood. Some researchers reported aging increasing RTN/WDF, while others showed RTN/WDF being hardly affected by aging. The objective of this work is to investigate the impact of hot carrier aging (HCA) on the RTN/WDF of nMOSFETs. For devices of average RTN/WDF, it is found that the effect of HCA is generally modest. For devices of abnormally high RTN/WDF, however, for the first time, we report HCA reducing RTN/WDF substantially (>50%). This reduction originates from either a change of current distribution or defect losses

Time-dependent variation: A new defect-based prediction methodology

For the first time, different impacts of as-grown and generated defects on nm-sized devices are demonstrated. As-grown hole traps are responsible for WDF, which increases with Vg_op and tw. The generated defects are substantial, but do not contribute to WDF and consequently are not detected by RTN. The non-discharging component follows the same model as that for large devices: the `AG' model. Based on this defect framework, a new methodology is proposed for test engineers to predict the long term TDV and yield and its prediction-capability is verified