48 research outputs found
Phase Farming with Trees: A report for the RIRDC/LWRRDC/FWPRDC Joint Venture Agroforestry Program
A scoping study was undertaken to determine the economic and biophysical feasibility of a proposal to research a system of phase farming with trees (PFT) in medium to low (300-600 mm) rainfall areas of southern Australia. This system is designed to use trees grown in very short term rotations (3-5 years) to rapidly de-water farming catchments, at risk of salinity, by depleting unsaturated stored soil water and reducing recharge while producing utilizable products. If feasible, the system will utilize a resource that is currently contributing to environmental problems while building more sustainable agricultural systems. Potential benefits include decreased salinization, improved farm cash flows, improved soil structure and acting as a disease and weed break..
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Radiation-hardened bulk CMOS technology
The evolutionary development of a radiation-hardened bulk CMOS technology is reviewed. The metal gate hardened CMOS status is summarized, including both radiation and reliability data. The development of a radiation-hardened bulk silicon gate process which was successfully implemented to a commercial microprocessor family and applied to a new, radiation-hardened, LSI standard cell family is also discussed. The cell family is reviewed and preliminary characterization data is presented. Finally, a brief comparison of the various radiation-hardened technologies with regard to performance, reliability, and availability is made
THE IMPORTANCE OF LANDSCAPE POSITION IN SCALING SVAT MODELS TO CATCHMENT SCALE HYDROECOLOGICAL PREDICTION
A low-V<inf>T</inf>N-channel enhancement mode IGFET for beam-lead sealed-junction technology
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Latch-up control in CMOS integrated circuits
The potential for latch-up, a pnpn self-sustaining low impedance state, is inherent in standard bulk CMOS structures. Under normal bias, the parasitic SCR is in its blocking state, but if subjected to a high-voltage spike or if exposed to an ionizing environment, triggering may occur. Prevention of latch-up has been achieved by lifetime control methods such as gold doping or neutron irradiation and by modifying the structure with buried layers. Smaller, next-generation CMOS designs will enhance parasitic action making the problem a concern for other than military or space applications alone. Latch-up control methods presently employed are surveyed. Their adaptability to VSLI designs is analyzed
