Signatures of the disk-jet coupling in the Broad-line Radio Quasar 4C+74.26

Here we explore the disk-jet connection in the broad-line radio quasar 4C+74.26, utilizing the results of the multiwavelength monitoring of the source. The target is unique in that its radiative output at radio wavelengths is dominated by a moderately-beamed nuclear jet, at optical frequencies by the accretion disk, and in the hard X-ray range by the disk corona. Our analysis reveals a correlation (local and global significance of 96\% and 98\%, respectively) between the optical and radio bands, with the disk lagging behind the jet by $250 \pm 42$ days. We discuss the possible explanation for this, speculating that the observed disk and the jet flux changes are generated by magnetic fluctuations originating within the innermost parts of a truncated disk, and that the lag is related to a delayed radiative response of the disk when compared with the propagation timescale of magnetic perturbations along relativistic outflow. This scenario is supported by the re-analysis of the NuSTAR data, modelled in terms of a relativistic reflection from the disk illuminated by the coronal emission, which returns the inner disk radius $R_{\rm in}/R_{\rm ISCO} =35^{+40}_{-16}$. We discuss the global energetics in the system, arguing that while the accretion proceeds at the Eddington rate, with the accretion-related bolometric luminosity $L_{\rm bol} \sim 9 \times 10^{46}$ erg s$^{-1}$ $\sim 0.2 L_{\rm Edd}$, the jet total kinetic energy $L_\textrm{j} \sim 4 \times 10^{44}$ erg s$^{-1}$, inferred from the dynamical modelling of the giant radio lobes in the source, constitutes only a small fraction of the available accretion power.Comment: 9 pages and 6 figures, ApJ accepte

Rapid and accurate leakage power estimation for nano-CMOS circuits

This paper addresses the crucial problem of static power reduction for circuits implemented in nano-CMOS technologies. Its solution requires accurate and rapid power estimation, but the known power simulators are not accurate and quick at the same time. The paper proposes and discusses a new rapid and very accurate leakage power estimation method and related simulator. The maximum estimation error of the simulator is within 5%, with an average error of only 0.57%, and run-times in the range of seconds, while for the same circuits HSPICE runs for hours or days

W.Pleskacz3, J.Raik4, R.Ubar4

A new fault model is developed for estimating the coverage of physical defects in digital circuits for given test sets. Based on this model, a new hierarchical defect oriented fault simulation method is proposed. At the higher level simulation we use the functional fault model, at the lower level we use the defectJault relationships in the form of defect coverage table and the defect probabilities. A description and the experimental data are given about probabilistic analysis of a complex CMOS gate. Analysis of the quality of 100 % stuck-at fault test sets for two benchmark circuits in covering physical defects like internal shorts, stuck-open 's and stuck-on 's. It has been shown that in the worst case a test with 100 % stuck-at fault coverage may have only 50 % coverage for internal shorts in complex CMOS gates. It has been shown that classical test coverage calculation based on counting defects without taking into account the defect probabilities may lead to considerable overestimation of results. 1