Rapid and accurate leakage power estimation for nano-CMOS circuits

This paper addresses the crucial problem of static power reduction for circuits implemented in nano-CMOS technologies. Its solution requires accurate and rapid power estimation, but the known power simulators are not accurate and quick at the same time. The paper proposes and discusses a new rapid and very accurate leakage power estimation method and related simulator. The maximum estimation error of the simulator is within 5%, with an average error of only 0.57%, and run-times in the range of seconds, while for the same circuits HSPICE runs for hours or days

W.Pleskacz3, J.Raik4, R.Ubar4

A new fault model is developed for estimating the coverage of physical defects in digital circuits for given test sets. Based on this model, a new hierarchical defect oriented fault simulation method is proposed. At the higher level simulation we use the functional fault model, at the lower level we use the defectJault relationships in the form of defect coverage table and the defect probabilities. A description and the experimental data are given about probabilistic analysis of a complex CMOS gate. Analysis of the quality of 100 % stuck-at fault test sets for two benchmark circuits in covering physical defects like internal shorts, stuck-open 's and stuck-on 's. It has been shown that in the worst case a test with 100 % stuck-at fault coverage may have only 50 % coverage for internal shorts in complex CMOS gates. It has been shown that classical test coverage calculation based on counting defects without taking into account the defect probabilities may lead to considerable overestimation of results. 1