A comparative study of the dry and wet nano-scale electro-machining

In recent years, a nano-electromachining (nano-EM) process based on a scanning tunneling microscope (STM) platform has been demonstrated. Nano-EM is capable of machining nano-features, under both, liquid dielectric (wet nano-EM) and air dielectric (dry nano-EM) media. The objective of this paper is to present a comparative study between the wet and dry nano-EM processes based on process mechanism, machining performance, consistency and dimensional repeatability of these two processes. The comparison of the two processes has been conducted at near field nano-EM, where the gap between the tool electrode and workpiece is 2 nm and the machining is performed at room temperature and pressure (macroscopically). The major differences in the process mechanism are due to the media at dielectric interface, the breakdown field strength and breakdown characteristics of two dielectrics and therefore, the material removal mechanism. It is reported that the material removal mechanism of wet nano-EM is associated with field emission-assisted avalanche in nano-confined liquid dielectric, whereas, the material removal mechanism in dry nano-EM is associated with field-induced evaporation of material. The differences have also been observed in the machining performance, dimensions of the machined features and repeatability of the nanoscale machined features. The self-tip-sharpening process with the continuation of machining has added several advantages to dry nano-EM over wet nano-EM in terms of dimensions of the nanoscale features, repeatability and machining performance

A comparative study of the dry and wet nano-scale electro-machining

In recent years, a nano-electromachining (nano-EM) process based on a scanning tunneling microscope (STM) platform has been demonstrated. Nano-EM is capable of machining nano-features, under both, liquid dielectric (wet nano-EM) and air dielectric (dry nano-EM) media. The objective of this paper is to present a comparative study between the wet and dry nano-EM processes based on process mechanism, machining performance, consistency and dimensional repeatability of these two processes. The comparison of the two processes has been conducted at near field nano-EM, where the gap between the tool electrode and workpiece is 2 nm and the machining is performed at room temperature and pressure (macroscopically). The major differences in the process mechanism are due to the media at dielectric interface, the breakdown field strength and breakdown characteristics of two dielectrics and therefore, the material removal mechanism. It is reported that the material removal mechanism of wet nano-EM is associated with field emission-assisted avalanche in nano-confined liquid dielectric, whereas, the material removal mechanism in dry nano-EM is associated with field-induced evaporation of material. The differences have also been observed in the machining performance, dimensions of the machined features and repeatability of the nanoscale machined features. The self-tip-sharpening process with the continuation of machining has added several advantages to dry nano-EM over wet nano-EM in terms of dimensions of the nanoscale features, repeatability and machining performance

Modification of mechanical properties of silicon nano-cantilevers by self ion implantation

Nanoscale silicon beams (similar to3 mum long, 250 nm wide, and 193 nm thick) were implanted with Si ions at energies of 100 and 35 keV and a dose of 1 x 10(15) ions/cm(2) and then tested using an atomic force microscope. The Young's modulus of fully amorphous silicon nanostructures (thus formed at 100 keV) was measured to be 134.5 GPa, and the modulus of bimaterial silicon nanostructures (amorphous and single crystal formed at 35 keV energy) was measured to be 150.3 GPa. Thus, the fundamental mechanical properties of 3D silicon nanostructures can be controllably modified using ion implantation at nanometer scale. This has major implications for nanoelectromechanical systems and related devices

Access devices for 3D crosspoint memory

The emergence of new nonvolatile memory (NVM) technologies-such as phase change memory, resistive, and spin-torque-transfer magnetic RAM-has been motivated by exciting applications such as storage class memory, embedded nonvolatile memory, enhanced solid-state disks, and neuromorphic computing. Many of these applications call for such NVM devices to be packed densely in vast "crosspoint" arrays offering many gigabytes if not terabytes of solid-state storage. In such arrays, access to any small subset of the array for accurate reading or low-power writing requires a strong nonlinearity in the IV characteristics, so that the currents passing through the selected devices greatly exceed the residual leakage through the nonselected devices. This nonlinearity can either be included explicitly, by adding a discrete access device at each crosspoint, or implicitly with an NVM device which also exhibits a highly nonlinear IV characteristic. This article reviews progress made toward implementing such access device functionality, focusing on the need to stack such crosspoint arrays vertically above the surface of a silicon wafer for increased effective areal density. The authors start with a brief overview of circuit-level considerations for crosspoint memory arrays, and discuss the role of the access device in minimizing leakage through the many nonselected cells, while delivering the right voltages and currents to the selected cell. The authors then summarize the criteria that an access device must fulfill in order to enable crosspoint memory. The authors review current research on various discrete access device options, ranging from conventional silicon-based semiconductor devices, to oxide semiconductors, threshold switch devices, oxide tunnel barriers, and devices based on mixedionic- electronic-conduction. Finally, the authors discuss various approaches for self-selected nonvolatile memories based on Resistive RAM. (c) 2014 American Vacuum Society.open1110681sciescopu

Nonvolatile memory crossbar arrays for non-von neumann computing

In the conventional vonNeumann (VN) architecture, data?both operands and operations to be performed on those operands?makes its way frommemory to a dedicated central processor.With the end of Dennard scaling and the resulting slowdown in Moore��s law, the IT industry is turning its attention to non-Von Neumann (non-VN) architectures, and in particular, to computing architectures motivated by the human brain. One family of such non-VN computing architectures is artificial neural networks (ANNs). To be competitive with conventional architectures, such ANNs will need to be massively parallel, with many neurons interconnected using a vast number of synapses,working together efficiently to compute problems of significant interest. Emerging nonvolatile memories, such as phase-change memory (PCM) or resistive memory (RRAM), could prove very helpful for this, by providing inherently analog synaptic behavior in densely packed crossbar arrays suitable for on-chip learning.We discuss our recent research investigating the characteristics needed from such nonvolatile memory elements for implementation of high-performance ANNs. We describe experiments on a 3-layer perceptron network with 164,885 synapses, each implemented using 2 NVM devices. A variant of the backpropagation weight update rule suitable for NVM+selector crossbar arrays is shown and implemented in a mixed hardware?software experiment using an available, non-crossbar PCM array. Extensive tolerancing results are enabled by precise matching of our NN simulator to the conditions of the hardware experiment. This tolerancing shows clearly that NVM-based neural networks are highly resilient to random effects (NVM variability, yield, and stochasticity), but highly sensitive to gradient effects that act to steer all synaptic weights. Simulations of ANNs with both PCM and non-filamentary bipolar RRAM based on Pr1?xCaxMnO3 (PCMO) are also discussed. PCM exhibits smooth, slightly nonlinear partial-SET (conductance increase) behavior, but the asymmetry of its abrupt RESET introduces difficulties; in contrast, PCMO offers continuous conductance change in both directions, but exhibits significant nonlinearities (degree of conductance change depends strongly on absolute conductance). The quantitative impacts of these issues on ANN performance (classification accuracy) are discussed. ? Springer (India) Pvt. Ltd. 2017.11Nscopu

Controlled removal of amorphous Se capping layer from a topological insulator

© 2014 AIP Publishing LLC. We report on the controlled removal of an amorphous Se capping layer from Bi2Te3 and Bi2Se3 topological insulators. We show that the Se coalesces into micron-sized islands before desorbing from the surface at a temperature of ∼150°C. In situ Auger Electron Spectroscopy reveals that Se replaces a significant fraction of the Te near the top surface of the Bi2Te3. Rutherford Backscattering Spectrometry and Transmission Electron Microscopy show that after heating, Se has been incorporated in the Bi2Te3 lattice down to ∼7 nm from its top surface while remaining iso-structural

Controlled removal of amorphous Se capping layer from a topological insulator

© 2014 AIP Publishing LLC. We report on the controlled removal of an amorphous Se capping layer from Bi2Te3 and Bi2Se3 topological insulators. We show that the Se coalesces into micron-sized islands before desorbing from the surface at a temperature of ∼150°C. In situ Auger Electron Spectroscopy reveals that Se replaces a significant fraction of the Te near the top surface of the Bi2Te3. Rutherford Backscattering Spectrometry and Transmission Electron Microscopy show that after heating, Se has been incorporated in the Bi2Te3 lattice down to ∼7 nm from its top surface while remaining iso-structural