Charged Particle Tracking in Real-Time Using a Full-Mesh Data Delivery Architecture and Associative Memory Techniques

We present a flexible and scalable approach to address the challenges of charged particle track reconstruction in real-time event filters (Level-1 triggers) in collider physics experiments. The method described here is based on a full-mesh architecture for data distribution and relies on the Associative Memory approach to implement a pattern recognition algorithm that quickly identifies and organizes hits associated to trajectories of particles originating from particle collisions. We describe a successful implementation of a demonstration system composed of several innovative hardware and algorithmic elements. The implementation of a full-size system relies on the assumption that an Associative Memory device with the sufficient pattern density becomes available in the future, either through a dedicated ASIC or a modern FPGA. We demonstrate excellent performance in terms of track reconstruction efficiency, purity, momentum resolution, and processing time measured with data from a simulated LHC-like tracking detector

Alignment strategy for the LHCb vertex locator

LHCb is one of the four main experiments of the Large Hadron Collider (LHC) project, which will start at CERN in 2008. The experiment is primarily dedicated to B-Physics and hence requires precise vertex reconstruction. These requirements place strict constraints on the LHCb vertex locator (VELO) alignment. Additional challenges arise from the VELO being retracted between each fill of the LHC and from its unique circular disc R/$\Phi$ strip geometry. This paper describes the software alignment procedure developed for the VELO, which is primarily based on a non-iterative method using a matrix inversion technique. The procedure is demonstrated with simulated events, and results obtained during runs in external test-beams are also presented

Le LHC vu des cuisines: De LHCb à CMS, en passant par ATLAS

Since my arrival at the CNRS in 2007, my activity has been part of the development and use of the results of the ATLAS and CMS experiments, two particle detectors currently in operation at CERN in Geneva. They are installed near the Large Hadron Collider (LHC), the most powerful particle accelerator ever built.ATLAS and CMS are complex assemblies used to detect and measure the properties (electric charge, momentum, energy) of particles created during the collision of protons circulating in the LHC. Each of these gigantic detectors contains approximately 100 million independent detection cells.The manuscript is mainly devoted to my activities within the CMS collaboration which I joined in 2010. I also briefly come back, in the first part, to my work within the ATLAS (2007-2010) and LHCb (2005-) collaborations. 2007). Since 2011 my work has mainly focused on updating this experience with a view to the ramp-up of the LHC in 2026. An adaptation of the collider and the detectors is indeed necessary to be able to collect 10 times more collision data. : this is the HL-LHC project. The next two parts are devoted to the upgrade of the future CMS tracker.Depuis mon arrivée au CNRS en 2007, mon activité s'inscrit dans le développement et l'exploitation des résultats des expériences ATLAS et CMS, deux détecteurs de particules actuellement en fonctionnement au CERN à Genève. Ils sont installés auprès du grand collisionneur de hadrons (LHC), l'accélérateur de particules le plus puissant jamais construit. ATLAS et CMS sont de complexes assemblages permettant de détecter et de mesurer les propriétés (charge électrique, quantité de mouvement, énergie) des particules créées lors de la collision des protons circulant dans le LHC. Chacun de ces gigantesques détecteurs contient environ 100 millions de cellules de détection indépendantes. Le manuscrit est essentiellement consacré à mes activités au sein de la collaboration CMS que j’ai rejoint en 2010. Je reviens également brièvement, dans la première partie, sur mes travaux au sein des collaborations ATLAS (2007-2010) et LHCb (2005-2007). Depuis 2011 mon travail est essentiellement axé autour de la remise à niveau de cette expérience en vue de la montée en puissance du LHC en 2026. Une adaptation du collisionneur et des détecteurs est en effet nécessaire pour pouvoir collecter encore 10 fois plus de données de collisions: c'est le projet HL-LHC. Les deux parties suivantes sont consacrées à la mise à niveau du futur trajectographe de CMS

CIC2 a radiation tolerant 65nm data aggregation ASIC for the future CMS tracking detector at LHC

The Concentrator Integrated Circuit (CIC) ASIC is a front-end chip for both Pixel-Strip (PS) and Strip-Strip (2S) modules of the future Phase-II CMS Outer Tracker upgrade at the High-Luminosity LHC (HL-LHC). This data aggregator, designed in 65nm CMOS technology, will be a key element of the tracker front-end chain. A first prototype, CIC1, was tested successfully in early 2019 and was followed by the development of a final radiation tolerant version of the chip: the CIC2. CIC2 design, implementation, and complete test results, are presented

A 65 nm Data Concentration ASIC for the CMS Outer Tracker Detector Upgrade at HL-LHC

International audienceThe Concentrator Integrated Circuit (CIC) ASIC is a front-end chip for both Pixel-Strip (PS) andStrip-Strip (2S) modules of the future Phase-II CMS Outer Tracker upgrade at the HighLuminosity LHC (HL-LHC). It collects the digital data coming from eight upstream front-endchips (either MPAs or CBCs, depending on the module type), formats the signal in data packetscontaining the trigger information from eight bunch crossings and the raw data from eventspassing the first trigger level, and finally transmits them to the LpGBT unit. The design and itsimplementation in a 65 nm CMOS technology of the first prototype that integrates allfunctionalities for system level operation are presented in this contribution

A System-Verilog Verification Environment for the CIC Data Concentrator ASIC of the CMS Outer Tracker Phase-2 Upgrades

International audienceThe foreseen Phase-2 upgrades at the LHC present very challenging requirements for the front-end readout electronics of the CMS Outer Tracker detector. High data rates in combination with the employment of a novel technique for rejecting locally low transverse momentum particles as well as the strict low power consumption constraints require the implementation of an optimized readout architecture and specific interconnect synchronization schemes for its components. This work focuses on the development and the verification of the Concentrator IC (CIC) ASIC, a 65 nm digital chip featuring high input and output data rates, in the context of the readout chains incorporating all front-end ASICs: namely the Macro Pixel ASIC (MPA), Short Strip ASIC (SSA) for the Pixel-Strip (PS) modules and the CMS Binary Chip (CBC) for Strip-Strip (2S) Modules. The CIC ASIC receives high data rate (320 MHz) digital streams from eight Front-end ASICs via a total of 48 differential lines and transmits them through seven differential lines operating at 320 MHz or 640 MHz, depending on the occupancy of the detector module. A complex system level simulation environment based on the System-Verilog hardware description language and on the Universal Verification Methodology (UVM) platform has been adapted and extended to help the CIC development and verification simulating the complete readout chains from the particle event to the output of the modules. The paper is composed of four sections: the first one describes the pT module concept, the second presents the UVM environment for MPA/SSA ASICs adapted and extended to include the CIC, the third one shows the readout-chain forecasted performances and show some examples of usage of this framework. The last section presents the PS module efficiency as a function of the stub occupancy for different CIC output frequencies

Study of a Triggered, Full Event Zero-Suppressed Front-End Readout Chain operating up to 1 MHz Trigger Rate and Pileup of 300 for CMS Outer Tracker upgrade at HL-LHC

International audienceThe CMS Outer Tracker at HL-LHC will have to cope with pileup of 300 events per bunch cross-ing and a trigger rate of up to 1 MHz. The front-end electronics readout chain consists of read-out ASICs connected to a data concentrator ASIC featuring zero-suppression. This contributionpresents the methodology and the analysis work for the buffer sizing and exception handling fea-turing a robust data readout synchronization, with an event loss probability lower than 0.1 % atthe highest pileup condition and a power density lower than 100 mW/cm$^2$

First results from the CIC data aggregation ASIC for the Phase 2 CMS Outer Tracker

The Concentrator Integrated Circuit (CIC) ASIC is a front-end chip for both Pixel-Strip (PS) and Strip-Strip (2S) modules of the future Phase 2 CMS Outer Tracker at the High-Luminosity LHC (HL-LHC). Prototyped in a 65 nm CMOS technology, the CIC aggregates the digital data coming from eight upstream front-end chips, formatting it into data packets containing the trigger information from eight bunch crossings and the raw data from events passing the Level 1 (L1) trigger, before transmission to the lpGBT. The role of the CIC in the readout chain is to provide an extra factor of data reduction by grouping data over time and space. A first prototype, the CIC1, integrating all functionalities for system level operation, has been tested in early 2019. A brief description of the functionalities and the test results obtained concerning the performance characterization and the radiation tolerance of the chip are presented in this contribution

Overview of LHCb alignment

In this report, we review the alignment strategy for the LHCb detector. We discuss the internal alignment stategy for each subdetector and the alignment of each of the subdetectors relative to one another