A network-on-chip monitoring infrastructure for communication-centric debug of embedded multi-processor SoCs

\u3cp\u3eProblems in a new System on Chip (SOC) consisting of hardware and embedded software often only show up when a silicon prototype of the chip is placed in its intended target environment and the application is executed. Traditionally, the debugging of embedded systems is difficult and time consuming because of the intrinsic lack of internal system observability and controlability in the target environment. Design for Debug (DfD) is the act of adding debug support to the design of a chip, in the realization that not every SOC is correct first time. DfD provides debug engineers with increased observability and controlability of the internal operation of an embedded system. In this paper, we present a monitoring infrastructure for multi-processor SOCs with a Network on Chip (NOC), and explain its application to performance analysis and debug. We describe how our monitors aid in the performance analysis and debug of the interactions of the embedded processors. We present a generic template for bus and router monitors, and show how they are instantiated at design time in our NOC design flow. We conclude this paper with details of their hardware cost.\u3c/p\u3

Component-level ASIL decomposition for automotive architectures

\u3cp\u3eThe Automotive industry is evolving towards a more electronics-assisted driving and self-driving functionality. The addition of complex subsystems has a great impact on the current vehicle architectures, leading to safety concerns. In this work we present a technique that follows the ISO 26262: Road Vehicles-Functional Safety standard to introduce redundancy in the architecture by using ASIL decomposition, and perform a safety analysis of the modelled system. A three-layer model is used to describe the application, the resources, and the physical space of the vehicle. In this paper we introduce novel model transformations to replicate parts of the application following ASIL decomposition rules. Finally, we perform a cost analysis and a probabilistic fault tree analysis on the architecture, making a comparison between different possible solutions. The advantages of these techniques, such as traceability and scalability, are shown by modelling and analysing the lateral control application of a real truck platooning system.\u3c/p\u3

A distributed architecture to check global properties for post-silicon debug

Post-silicon validation and debug, or ensuring that software executes correctly on the silicon of a multi-processor system-on-chip (MPSOC) is complicated, as it involves checking global properties that are distributed on the chip. In this paper we define an architecture to non-intrusively observe global properties at run time using distributed monitors. The architecture enables to perform actions when a property holds, such as stopping (part of) the system for inspection. We apply this architecture to the problem of software races that result in incorrect communication between concurrent tasks on different processors. In a case study, where we implemented monitors, event distribution, and instruments to stop communication between intellectual property (IP) blocks, we demonstrate that these races can be detected and classified as timing violations or as FIFO protocol violations

Optimal interconnect ATPG under a ground-bounce constraint

In order to prevent ground bounce, automatic test pattern generation (ATPG) algorithms for wire interconnects have recently been extended with the capability to restrict the maximum Hamming distance between any two consecutive test patterns to a user-defined integer, referred to as simultaneously-switching outputs limit (SSOL). The conventional approach to meet this SSOL constraint is to insert additional test patterns between consecutive test patterns if their Hamming distance is too large; this approach often leads to many more test patterns than strictly necessary. This paper presents an algorithm that generates, for a user-defined number of interconnect wires, a minimal set of test patterns that respect a user-defined SSOL constraint. Experimental results show that, in comparison to the conventional approach, our algorithm leads to a significant reduction in the test pattern count and corresponding test application time. For example, for problem instances with 5000, 6000, 7000, and 8000 wires, the algorithm reduces the corresponding test application time on average with 45%

Optimal interconnect ATPG under a ground-bounce constraint

In order to prevent ground bounce, Automatic Test Pattern Generation (ATPG) algorithms for wire interconnects have recently been extended with the capability to restrict the maximal Hamming distance between any two consecutive test patterns to a user-defined integer, referred to as the Simultaneously-Switching Outputs Limit (SSOL). The conventional approach to meet this SSOL constraint is to insert additional test patterns between consecutive test patterns if their Hamming distance is too large; this approach often leads to substantially more test patterns than strictly necessary. This paper presents an algorithm that generates, for a user-defined number of interconnect wires, a minimal set of test patterns that respects a user-defined SSOL constraint. Experimental results show that, in comparison to the conventional approach, our algorithm leads to a significant reduction of up to 60% in the test pattern count and corresponding test application time

Test and debug features of the RTO7 chip

The Philips RTO7 chip consists of a complete receive chain from RF up to and including digital demodulation for Bluetooth-like radio communication. This paper describes both the implementation and verification of the test and debugs hardware for the digital core of the RTO7. The core-based DfT and DfD flow of the RTO7 is presented. The experimental results show that the RTO7 is both a fully testable and debuggable chip. State dump analysis results are also presented, showing that the state dumps obtained in the application are 100% stable, and match the state dumps made in simulation, and on the digital test syste

Minimizing pattern count for interconnect test under a ground bounce constraint

When testing the interconnect structures on a board, test programmers sometimes ask, How can I control the test pattern generation process to avoid ground bounce problems during Extest mode? Those wishing to satisfy a simultaneously-switching-outputs constraint will find several new solutions in this article

Creating value through test

Test is often seen as a necessary evil; it is a fact of life that ICs have manufacturing defects and those need to be filtered out by testing before the ICs are shipped to the customer. In this paper, we show that techniques and tools used in the testing field can also be (re-)used to create value to (1) designers, (2) manufacturers, and (3) customers alike. First, we show how the test infrastructure can be used to detect, diagnose, and correct design errors in prototype silicon. Secondly, we discuss how test results are used to improve the manufacturing process and hence production yield. Finally, we present test technologies that enable systems of high reliability for safety-critical applications