4 research outputs found

    Robustness Analysis for Value-Freezing Signal Temporal Logic

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    In our previous work we have introduced the logic STL*, an extension of Signal Temporal Logic (STL) that allows value freezing. In this paper, we define robustness measures for STL* by adapting the robustness measures previously introduced for Metric Temporal Logic (MTL). Furthermore, we present an algorithm for STL* robustness computation, which is implemented in the tool Parasim. Application of STL* robustness analysis is demonstrated on case studies.Comment: In Proceedings HSB 2013, arXiv:1308.572

    On Parameter Synthesis by Parallel Model Checking

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