The improvement of Mo/4H-SiC Schottky diodes via a P2O5 surface passivation treatment

Molybdenum (Mo)/4H-silicon carbide (SiC) Schottky barrier diodes have been fabricated with a phosphorus pentoxide (P2O5) surface passivation treatment performed on the SiC surface prior to metallization. Compared to the untreated diodes, the P2O5-treated diodes were found to have a lower Schottky barrier height by 0.11 eV and a lower leakage current by two to three orders of magnitude. Physical characterization of the P2O5-treated Mo/SiC interfaces revealed that there are two primary causes for the improvement in electrical performance. First, transmission electron microscopy imaging showed that nanopits filled with silicon dioxide had formed at the surface after the P2O5 treatment that terminates potential leakage paths. Second, secondary ion mass spectroscopy revealed a high concentration of phosphorus atoms near the interface. While only a fraction of these are active, a small increase in doping at the interface is responsible for the reduction in barrier height. Comparisons were made between the P2O5 pretreatment and oxygen (O2) and nitrous oxide (N2O) pretreatments that do not form the same nanopits and do not reduce leakage current. X-ray photoelectron spectroscopy shows that SiC beneath the deposited P2O5 oxide retains a Si-rich interface unlike the N2O and O2 treatments that consume SiC and trap carbon at the interface. Finally, after annealing, the Mo/SiC interface forms almost no silicide, leaving the enhancement to the subsurface in place, explaining why the P2O5 treatment has had no effect on nickel- or titanium-SiC contacts

A compact trench-assisted space-modulated JTE design for high-voltage 4H-SiC devices

This article proposes a compact trench-assisted space-modulated junction termination extension (TSM-JTE) design for high-voltage 4H-silicon carbide (SiC) devices. In this design, trench structures are introduced into the JTE region to effectively split the termination region into three functional zones. The proposed termination structure is cost effective in terms of the chip area it occupies; for devices rated at 10 kV, the termination structure extends the edge of the device by only 250 μm. Requiring only one implant, it is relatively cheap to fabricate, while a wide implantation dose window endures that is relatively insensitive to variations in dose that may occur during processing. The same advantages occur at 20 kV, the TSM-JTE proving to have the best tradeoff between maximum breakdown voltage and implantation window, compared with other single implant termination designs, achieving this in 500 μm of termination length. At 3.3 kV, a 110-μm TSM-JTE retains its advantages over the other JTE designs, but floating field rings are expected to consume less area, though this is not the case at the higher voltages

Initial investigations into the MOS interface of freestanding 3C-SiC layers for device applications

This letter reports on initial investigation results on the material quality and device suitability of a homo-epitaxial 3C-SiC growth process. Atomic force microscopy surface investigations revealed root-mean square surface roughness levels of 163.21 nm, which was shown to be caused by pits (35 μm width and 450 nm depth) with a density of 1.09 × 105 cm−2 which had formed during material growth. On wider scan areas, the formation of these were seen to be caused by step bunching, revealing the need for further epitaxial process improvement. X-ray diffraction showed good average crystalline qualities with a full width of half-maximum of 160 arcseconds for the 3C-SiC (002) being lower than for the 3C-on-Si material (210 arcseconds). The analysis of C–V curves then revealed similar interface-trapped charge levels for freestanding 3C-SiC, 3C-SiC on Si and 4H-SiC, with forming gas post-deposition annealed freestanding 3C-SiC devices showing DIT levels of 3.3 × 1011 cm−2 eV−1 at EC−ET = 0.2 eV. The homo-epitaxially grown 3C-SiC material's suitability for MOS applications could also be confirmed by leakage current measurements

The optimization of 3.3 kV 4H-SiC JBS diodes

The article reports a comprehensive study optimizing the OFF- and ON-state characteristics of 3.3 kV junction barrier Schottky (JBS) diodes made using nickel, titanium, and molybdenum contact metals. In this design, the same implants used in the optimized termination region are used to form the P-regions in the JBS active area. The width and spacing of the P-regions are varied to optimize both the ON- and OFF-state of the device. All the diodes tested displayed high blocking voltages and ideal turn-on characteristics up to the rated current of 2 A. However, the leakage current and the Schottky barrier height (SBH) were found to scale with the ratio of Schottky to p + regions. Full Schottkys, without p + regions, and those with very wide Schottky regions had the lowest SBH (1.61 eV for Ni, 1.11 eV for Mo, and 0.87 eV for Ti) and the highest leakage. Those diodes with the lowest Schottky openings of 2 μm had the lowest OFF-state leakage, but they suffered severe pinching from the surrounding p + regions, increasing their SBH. The best performing JBS diodes were Ni and Mo devices with the narrowest pitch, with the p + implants/Schottky regions both 2 μm wide. These offered the best balanced device design, with excellent OFF-state performance, while the Schottky ratio guaranteed a relatively low forward voltage drop

Silicon carbide and related materials 2018

12th European Conference on Silicon Carbide and Related Materials (ECSCRM 2018) Selected, peer reviewed papers from the European Conference on Silicon Carbide and Related Materials (ECSCRM 2018), September 2-6, 2018,Birmingham, UK

Data for Effect of HCl cleaning on InSb–Al2O3 MOS capacitors

In this work, the role of HCl treatments on InSb surfaces and InSb–Al2O3 dielectric interfaces is characterised. X-ray photoelectron spectroscopy measurements indicate that HCl diluted in and rinsed with isopropanol (IPA) results in a surface layer of InCl3 which is not present for similar HCl-water processes. Furthermore, this InCl3 layer desorbs from the surface between 200 °C and 250 °C. Metal–oxide–semiconductor capacitors were fabricated using atomic layer deposition of Al2O3 at 200 °C and 250 °C and the presence of InCl3 was associated with a +0.79 V flatband voltage shift. The desorption of the InCl3 layer at 250 °C reversed this shift but the increased process temperature resulted in increased interface-trapped charge (D it) and hysteresis voltage (V H ). This shift in flatband voltage, which does not affect other figures of merit, offers a promising route to manipulate the threshold voltage of MOS transistors, allowing enhancement-mode and depletion-mode devices to be fabricated in parallel

The optimisation, fabrication and comparison of 10 kV-rated 4H-SiC IGBTs and MOSFETs

The authors report on a range of 10 kV SiC IGBTs that are being developed, deploying a novel retrograde p-base to maximise device ruggedness, thus minimizing the amount of derating required. These devices are being developed alongside a set of 10 kV SiC MOSFETs with the same active area splits, allowing for a thorough comparison between unipolar and bipolar device action at this voltage level. Initial results of blocking voltage and on-state measurements validate the front-side process and allow for exploration of the trade-offs. A significant reduction of specific on-resistance in measured IGBTs, compared to their MOSFET counterparts, could be demonstrated at this voltage level, along the blocking voltage ability

A study of high resistivity semi-insulating 4H-SiC epilayers formed via the implantation of Germanium and Vanadium

A systematic germanium (Ge) and vanadium (V) study on 4H-SiC epitaxial layers is presented. Electrical results of TLM structures which were fabricated on these layers revealed that highly-doped Ge and V-implanted layers showed extremely low specific contact resistivity, down to 2 x 10-7 Ω.cm2. Current flow in the conducting state of Schottky barrier diodes has been successfully suppressed in some implanted layers, with highly V doped samples showing current density values of approximately 1 x 10-5 Acm-2 at 10 V. DLTS spectra reveal the presence of germanium and vanadium centers in the respective samples as well as novel peaks which are likely related to the formation of a novel GeN center

The improved reliability performance of post-deposition annealed ALD-SiO2

A systematic capacitance-voltage (C-V) and time-dependent dielectric breakdown (TDDB) study on silicon carbide (SiC) metal-oxide-semiconductor capacitors (MOSCAPs) that use silicon dioxide (SiO2) is shown in this paper. Oxides were formed using atomic layer deposition (ALD), low-pressure chemical vapour deposition (LPCVD) or direct thermal growth in nitrous oxide (N2O) ambient, where both deposited oxides were post-deposition annealed in N2O ambient, too. The electrical characterisation results reveal that the ALD-deposited and N2O-annealed oxides show the best capacitance-voltage (C-V) characteristics, with flatband and hysteresis voltages (VFB) averaging 1.44 V and 0.41 V, respectively. When measuring the leakage current levels at 175°C, the ALD-deposited MOSCAPs’ breakdown electric fields are averaging similar to their counterparts at 9.71 MV/cm. MOSCAPs which utilized ALD-deposited SiO2 also showed 29% and 345% increased average injected charge-to 63% failure (QBD,63%) at 9 MV/cm and 9.6 MV/cm, respectively, when comparing these devices to their direct thermally grown SiO2 counterparts