Analysis of textured films and periodic Grating Structures with Mueller Matrices: A new Challenge in Instrumentation with the generation of angle-resolved SE polarimeters

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Overlay measurements by Mueller polarimetry in back focal plane

International audienceAngle resolved Mueller polarimetry implemented as polarimetric imaging of a back focal plane of a high NA microscope objective has already demonstrated a good potential for CD metrology. Here we present the experimental and numerical results indicating that this technique may also be competitive for the measurements of overlay error delta. A series of samples of superimposed gratings with well controlled overlay errors have been manufactured and measured with the angle resolved Mueller polarimeter. The overlay targets were 20-mu m wide. When the overlay error is delta is equal to 0, absolute values of elements of real 4x4 Mueller matrix M are invariant by matrix transposition. Otherwise this symmetry breaks down. Consequently, we define the following overlay estimator matrix as E = |M| - |M|(t). The simulations show that matrix element E-14 is the most sensitive to the overlay error. The scalar estimator of E-14 was calculated by averaging the pixel values over a specifically chosen mask. This estimator is found to vary linearly with d for overlay values up to 50 nm. Our technique allows entering small overlay marks (down to 5-mu m wide). Only one target measurement is needed for each overlay direction. The actual overlay value can be determined without detailed simulation of the structure provided two calibrated overlay structures are available for each direction

Highly sensitive detection technique of buried defects in extreme ultraviolet masks using at-wavelength scanning dark-field microscopy

A technique to probe defects buried inside extreme ultraviolet EUV masks has been implemented using a dark-field microscopy detection setup. Specific samples have been fabricated to evaluate the sensitivity of this technique. They consist of silicon oxide gratings of a few nanometers height, coated with 40 layer pairs of molybdenum\u2013silicon. We observed images with a good contrast on samples with defects as low as 3 nm. However, the imaging mechanism of scanning dark-field microscopy is not linear and can produce image distortions. Conditions of correct imaging have been analyzed, and simulations have been performed that show good agreement with the experimental data. This work opens the way for a better understanding of the capability of at-wavelength inspection technique for EUV mask

Die-to-die alignment for lithographic processing of reconstructed wafers

International audienceIn this work, we address one of the challenges of Fan-Out Wafer Level Packaging (FO-WLP), which is chip placement error, which occurs during the process of wafer reconstruction and molding. In a typical FO-WLP process, a wafer processed on a front-end tool is diced, and the dies are repositioned on a carrier with additional space created for fan-out structures. A dedicated alignment approach, which includes measurement of individual dies to adjust the settings per exposure, would result in a dramatic improvement of the overlay performance. This process further referred to as die-to-die alignment is generally known to have negative impact on throughput for IC manufacturers.The accuracy of die-to-die alignment on 200 mm wafers is evaluated experimentally in collaboration between Kulicke & Soffa and CEA LETI. The wafer layout consists of dies of different sizes (120 chips of 4 mm x 4 mm and 70 of 10 mm x 10 mm) for which intentional misalignments have been introduced with different amounts of translation (up to +/-50 micrometers) and rotation (up to +/-10 milliradians) in order to emulate typical errors found in reconstructed wafers.Alignment of the "back-end" layer with respect to existing patterns on the wafer was measured both at Kulicke & Soffa and at CEA LETI. Both measurements confirmed sub-micrometer accuracy of overlay between the structures on the reference wafer and the new layer exposed on LITEQ 500. Throughput in-line with current industrial standards was achieved. Data analysis shows that major improvements of the throughput can be achieved by optimizing the exposure process

Analytic model of Vth recovery in MISGate recess high electron mobility transistor after blocking voltage stress

International audienceToday wide band gap (WBG) material are consider as future brick allowing improvement of power transistor in order to reduce conduction lost as well as switching loses. Two kind of WBG are in concurrence SiC and GaN. For economical reason, several researches are particularly fo-cused on GaN on silicon. The main advantage of GaN is the capability to use a two-dimensional electron gaz (2Deg) as conduction layer but the transistors using this 2Deg are naturally normally on. Several solution are proposed to make it normally off and one of these is the usage of gate re-cess (allowing to cut physically the 2Deg). This work provide an analytical model of Vth evolution in MISGATE (metal insulator gate) GaN transistor on silicon. It has been shown that the main impact is due to charges close to the gate oxide (Al2O3 and AlN/AL2O3) interface and GaN charges. This model allows extracting traps energy levels from threshold voltage (Vth) re-covery curve in the time after a 650V stress. It has been possible to extract up to four different traps energies levels

Normally-OFF 650V GaN-on-Si MOSc-HEMT Transistor: Benefits of the fully recessed gate architecture

International audienceIn this paper we present a detailed performance status of AlGaN/GaN MOS channel High Electron Mobility Transistors (MOSc HEMTs) with fully recessed gate architecture on 200mm Si substrates. We report a wide range of wafer and package level results. ON state resistance is studied through three aspects: i) RON partitioning with analysis of its four components, ii) RON temperature dependence, iii) cumulative dynamic RON under stress. For accurate power assessment we characterize packaged devices and compare the typical figures of merit (gate charge, switching tests) to state of the art references (especially pGaN gate HEMTs). We highlight the benefits offered by this technology for 650V applications, such as very low IGSS leakage even at 150°C, and better switching performances, td(on), td(off)