Analog test interface for IEEE 1687 employing split SAR architecture to support embedded instrument dependability applications

Embedded instruments have become ubiquitous in modern day System-on-Chips for test and monitoring purposes. IEEE 1687 or IJTAG addresses the standardization of access and operation of these embedded instruments. Recently, there has been a lot of interest in employing embedded instruments for dependability purposes. Many of these embedded instruments are required to monitor physical quantities which are analog in nature. A cost-effective architecture to integrate these analog instruments into the IEEE 1687 infrastructure is a bottleneck and has not yet been standardized. This paper presents a time and area efficient architecture to interface analog embedded instruments onto the IEEE 1687 network especially for dependability applications. The architecture mitigates the drawbacks associated with utilizing an analog test bus and enables periodic sampling with minimal hardware overhead. The simulations to illustrate the concept have been conducted with TSMC 40nm CMOS technology