33 research outputs found

    Design of a QCA memory with parallel read/serial write

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    Secure Lightweight IoT Integrated RFID Mobile Healthcare System

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    Patient safety is a global public health concern nowadays, especially in elderly people who need physiological health monitoring systems integrated with a technology which will help to oversee and manage the medical needs. In this direction, we propose a lightweight effective healthcare monitoring system designed by using the Internet of Things (IoT) and Radio Frequency Identification (RFID) tags. In this technique, we use dual-band RFID protocols which are the one working at a high frequency of 13.56 MHz and useful to figure out the individuals, and 2.45 GHz microwave bands are used to monitor corporal information. Sensors are used to monitor and collect patient physiological data; RFID tag is used to recognize the patient. This IoT-based RFID healthcare monitoring system provides acquisition of physiological information of elderly people and patients in hospital. Further, it is aiming to secure patient’s health recordings using hyper elliptic curve- (HEC-) based signcryption algorithm while allowing the doctor to access patient health information. Privacy is provided to variable length patient medical records using different genus curves, and the evaluation shows that the proposed algorithm is optimal with respect to healthcare

    QCA memory with parallel read/serial write: design and analysis

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    This paper presents a novel memory architecture for implementation by Quantum-dot Cellular Automata (QCA). The proposed architecture combines the advantages of reduced area of a serial memory with the reduced latency in the read operation of a parallel memory. An extensive evaluation with respect to latency and area is pursued. For area analysis, a novel characterization which considers cells in the logic circuitry, interconnect as well as the unused portion of the Cartesian place as QCA layout, is proposed. 1 Summary and conclusions Our proposed novel memory architecture for QCA implementation utilizes a parallel read operation on multiple bit loops. The memory arrangement is referred to as “hybrid” due to the different operational mechanism for the tw
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