Optimization of single halo p-MOSFET implant parameters for improved analog performance and reliability

The effect of Channel Hot Carrier (CHC) stress under typical analog operating conditions is studied for p-MOSFETs. Our detailed characterization results show that Single Halo devices not only show improved performance, but also are immune to CHC degradation under various operating conditions

A novel dry method for surface modification of SU-8 for immobilization of biomolecules in Bio-MEMS

SU-8 has been primarily used for structural elements and microfludics components in MEMS. Microsystems for biological applications require immobilization of biomolecules on the MEMS structures. In order to functionalize SU-8 for such purposes, the surface needs to be modified. In this paper, we report a novel dry method of surface modification of SU-8 which is compatible with standard microfabrication techniques. The surface obtained by spin coating SU-8 (2002) on silicon wafer was modified by grafting amine groups using pyrolytic dissociation of ammonia in a hotwire CVD setup. To demonstrate the presence of amine groups on modified SU-8 surface, the surface characteristic after modification was assessed using Fourier transform infrared spectroscopy. The change in SU-8 surface morphology before and after surface modification was investigated using atomic force microscopy. To show the utility of this process for application in Bio-MEMS, SU-8 microcantilevers were fabricated and subjected to the same surface modification protocol. Following this, the cantilevers were incubated first in a suspension of human immunoglobulin (HIgG) and then in FITC tagged goat anti-human IgG in order to demonstrate the utility of the surface modification performed. The efficacy of the process was assessed by observing the cantilevers under a fluorescence microscope

Morphology and Curie temperature engineering in crystalline La0.7Sr0.3MnO3 films on Si by pulsed laser deposition

Of all the colossal magnetoresistant manganites, La0.7Sr0.3MnO3 (LSMO) exhibits magnetic and electronic state transitions above room temperature, and therefore holds immense technological potential in spintronic devices and hybrid heterojunctions. As the first step towards this goal, it needs to be integrated with silicon via a well-defined process that provides morphology and phase control, along with reproducibility. This work demonstrates the development of pulsed laser deposition (PLD) process parameter regimes for dense and columnar morphology LSMO films directly on Si. These regimes are postulated on the foundations of a pressure-distance scaling law and their limits are defined post experimental validation. The laser spot size is seen to play an important role in tandem with the pressure-distance scaling law to provide morphology control during LSMO deposition on lattice-mismatched Si substrate. Additionally, phase stability of the deposited films in these regimes is evaluated through magnetometry measurements and the Curie temperatures obtained are 349 K (for dense morphology) and 355 K (for columnar morphology)-the highest reported for LSMO films on Si so far. X-ray diffraction studies on phase evolution with variation in laser energy density and substrate temperature reveals the emergence of texture. Quantitative limits for all the key PLD process parameters are demonstrated in order enable morphological and structural engineering of LSMO films deposited directly on Si. These results are expected to boost the realization of top-down and bottom-up LSMO device architectures on the Si platform for a variety of applications. (C) 2014 AIP Publishing LLC

A novel dynamic threshold operation using electrically induced junction MOSFET in the deep sub-micrometer CMOS regime

The desired low power and high speed operation of CMOS integrated circuits is driving force for CMOS scaling into the sub-100 nm regime. In addition to the supply voltage, the threshold voltage needs to be scaled proportionately for low power operation. The idea of a Dynamic Threshold MOSFET (DTMOS), without the associated substrate loading effects, is a key to the problems involved in Sub-100 nm device scaling for low power CMOS. This work focuses on the device optimisation for such low power ULSI circuits using a novel implementation of Electrically Induced Junction (EJ)-MOSFET as a DTMOS. Such an implementation can be used without the additional substrate loading effects and the supply voltage limitations, commonly associated with conventional DTMOS operation. Our detailed DC as well as transient simulation results bring out the advantages of this novel structure.© IEE

Analog circuit performance issues with aggressively scaled gate oxide CMOS technologies

MOS transistors with sub 100 nm channel lengths need a gate oxide thickness in the range of 1-2 nm to combat the short channel effects. However at these gate dielectric thicknesses, the gate current is no longer negligible. In this paper, we report the device analog behavior with extremely scaled oxides for integrating mixed signal circuits using the scaled digital CMOS technologies. We show the performance of common source amplifiers and current mirror circuits with these technologies. Our results also show that though thin oxides result in good voltage gains of amplifier circuits, the increased gate leakage degrades the performance of current mirror circuits. We also analyze the performance of different classes of current mirror circuits in the presence of gate leakage and provide broad guidelines for analog circuit design in the presence of gate leakage.© IEE

Forward body-biased single halo MOS devices for low voltage analog circuits

Forward body bias has been shown to be an effective way to improve the digital performance of CMOS circuits. However, as the technologies scale into the sub 100 nm regime, body bias sensitivity degrades, making the application of body bias less attractive for scaled CMOS technologies. In this work, we show for the first time that, Single Halo (SH) MOSFETS exhibit superior body bias sensitivity in the sub 100 nm regime compared to conventional technologies, which can be utilized for improving the performance of forward body-biased MOS devices such as dynamic threshold (DTMOS) and body-driven (BDMOS) transistors for low-voltage (LV) analog designs with the scaled technologies. Our result show that SH doping in these devices results in more than 50 % improvement of intrinsic gain and about a factor of two improvement in transconductance for DTMOS and BDMOS devices respectively, compared to their conventional counterparts.© IEE

Sub-threshold swing degradation due to localized charge storage in SONOS memories

This paper discusses the effect of localized charge storage on sub-threshold swing and threshold voltage in silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory cells. By analyzing the change in potential contours, it has been shown that the change in sub-threshold swing is correlated to fringing of electric field lines, and hence to the gate-to-substrate capacitance.© IEE