Simulating the Effects of Skin Thickness and Fingerprints to Highlight Problems with Non-invasive RF Blood Glucose Sensing from Fingertips

The non-invasive measurement of blood glucose is a popular research topic where RF/microwave sensing of glucose is one of the promising methods in this area. From the many available measurement sites in the human body, fingertips appear to be a good choice due to a good amount of fresh blood supply and homogeneity in terms of biological layers present. The non-invasive RF measurement of blood glucose relies on the detection of the change in the permittivity of the blood using a resonator as a sensor. However, the change in the permittivity of blood due to the variation in glucose content has a limited range resulting in a very small shift in the sensor’s frequency response. Any inconsistency between measurements may hinder the measurement results. These inconsistencies mostly arise from the varied thickness of the biological layers and variation of fingerprints that are unique to every human. Therefore, the effects of biological layers and fingerprints in fingertips were studied in detail and are reported in this paper

A Novel Pressure Sensing Circuit for Non-invasive RF/Microwave Blood Glucose Sensors

A novel pressure sensing circuit for non-invasive RF/microwave blood glucose sensors is presented in this paper. RF sensors are of interest to researchers for measuring blood glucose levels non-invasively. For the measurements, the finger is a popular site that has a good amount of blood supply. When a finger is placed on top of the RF sensor, the electromagnetic fields radiating from the sensor interact with the blood in the finger and the resulting sensor response depends on the permittivity of the blood. The varying glucose level in the blood results in a permittivity change causing a shift in the sensor’s response. Therefore, by observing the sensor’s frequency response it may be possible to predict the blood glucose level. However, there are two crucial points in taking and subsequently predicting the blood glucose level. These points are; the position of the finger on the sensor and the pressure applied onto the sensor. A variation in the glucose level causes a very small frequency shift. However, finger positioning and applying inconsistent pressure have more pronounced effect on the sensor response. For this reason, it may not be possible to take a correct reading if these effects are not considered carefully. Two novel pressure sensing circuits are proposed and presented in this paper to accurately monitor the pressure applied

All-Digital 1550 nm Optical Aqueous Glucose Solution Measurement System

An all-digital 1550 nm optical measurement system is proposed for measuring the concentration of aqueous solutions of glucose to investigate the feasibility of NIR blood glucose measurements. A microcontroller was used to generate the excitation signal for a 1550 nm laser module as well as generate the reference signal to perform the lock-in amplifier function. A sine wave was generated inside the firmware to drive the laser module through a current DAC. The reference signal was generated by reading the monitor diode inside the laser module through the microcontroller’s internal ADC. A cooled photodetector was used to measure the light level where its output was digitized by a 24-bit ADC after analog signal conditioning. The glucose concentration result for the measurement was calculated performing DSP functions using the mentioned signals as set out in this paper. A correlation was successfully observed between measured signal level and glucose concentration

Permittivity Extraction of Glucose Solutions Through Artificial Neural Networks and Non-invasive Microwave Glucose Sensing

An accurate low-cost method is presented for measuring the complex permittivity of glucose/water solutions. Moreover, a compact non-invasive RF/microwave sensor is presented for glucose sensing with the reasoning behind design parameters as well as simulation and measurement results. The complex permittivity values of aqueous solutions of glucose were measured with an in-house manufactured open-ended coaxial probe and the values were extracted from the measured complex reflection coefficients (S11) utilizing artificial neural networks. The obtained results were validated against a commercial probe. The values were fitted to the Debye relaxation model for ease of evaluation for a desired glucose concentration at a desired frequency. The proposed permittivity model in this paper is valid for glucose concentrations of up to 16 g/dl in the 0.3–15 GHz range. The model is useful for simulating and validating non-invasive RF glucose sensors

Experimentation with Strategy and the Evolution of Dynamic Capability in the Indian Pharmaceutical Sector

This paper demonstrates that radical regulatory changes can be tantamount to technological revolutions by studying Indian pharmaceutical firms. It shows that radical regulatory changes such as the Indian Patent Act of 1970, the New Industrial Policy of 1991 and the signing of TRIPS (Trade Related Intellectual Property Rights System) in 1995 served to open up new economic opportunities and constraints in the wake of which the winners and losers were selected as a function of the dynamic firm capabilities most appropriate for the new market environment.International Marketing, R&D Management, India, Pharmaceutical Sector, Corporate Strategy

Symmetric Power Analysis Attack Resilient Adiabatic Logic for Smartcard Applications

On the whole existing secure adiabatic logic designs exhibit variations in current peaks and have asymmetric structures. However, asymmetric structure and variations in current peaks make the circuit vulnerable to Power Analysis Attacks (PAA). In this paper, we shall present a novel PAA resilient adiabatic logic which has a symmetric structure and exhibits the least variations in current peaks for basic gates as well as in 8-bit Montgomery multiplier. The proposed logic has been compared with two recently proposed secure adiabatic logic designs for operating frequencies ranging from 1MHz to 100MHz and power-supply scaling ranging from 0.6V to 1.8V. Simulation results of the gates show that our proposed logic exhibits the lowest Normalized Energy Deviation (NED) and Normalized Standard Deviation (NSD) under the said frequency variations. All the 2-input gates that deploy the proposed logic dissipate nearly the same average energy within 0.2% of each other at all the frequencies simulated and thus, along with the dataindependence,gate-function-independence is achieved. The paper will also report on the energy dissipated by the proposed logic which approaches that of the existing logic designs as the output load capacitance is increased above 100fF. The simulation results of the 8-bit adiabatic Montgomery multiplier show that the proposed logic exhibits the least value of NED and NSD under the said frequency variations and power-supply scaling. Finally, the paper will report on the current waveform graphs for variations in current peaks under power-clock scaling

Adiabatic Flip-Flops and Sequential Circuit Design using Novel Resettable Adiabatic Buffers

We propose novel resettable adiabatic buffers for five adiabatic logic families namely; Efficient Adiabatic Charge Recovery Logic (EACRL), Improved Efficient Charge Recovery Logic (IECRL), Positive Feedback Adiabatic Logic (PFAL), Complementary Pass-transistor Adiabatic Logic (CPAL) and Clocked Adiabatic Logic (CAL). We present the design of resettable flip-flops using the proposed buffers. The proposed flip-flops alleviate the problem of increased energy and area consumption incurred by the existing mux-based resettable flip-flops. We then design the 3-bit up-down counters and extended our comparison beyond energy dissipation using the above five adiabatic logic families. PFAL based sequential circuit designs gives the best performance trade-offs in terms of complexity, energy, speed and area compared to the other adiabatic designs

Robustness of Power Analysis Attack Resilient Adiabatic Logic: WCS-QuAL under PVT Variations

In this paper, we propose Without Charge Sharing Quasi Adiabatic Logic (WCS-QuAL) as a countermeasure against Power Analysis Attacks. We evaluate and compare our logic with the recently proposed secure adiabatic logic designs SPGAL and EE-SPFAL at frequencies ranging from 1MHz to 100MHz. Simulation results show that WCS-QuAL outperforms the existing secure adiabatic logic designs on the basis of % Normalized Energy Deviation (NED) and % Normalized Standard Deviation (NSD) at all simulated frequencies. Also, all 2-input gates using WCS-QuAL dissipate nearly equal energy for all possible input transitions. In addition, the energy dissipated by WCS-QuAL approaches to the energy dissipation of EESPFAL and SPGAL as the output load capacitance is increased above 100fF. To further evaluate and compare the performance, GF (24) bit-parallel multiplier was implemented as a design example. The impact of Process-Voltage-Temperature (PVT) variations, power supply scaling and technology on the performance of the three logic designs was investigated and compared. Simulation results show that WCS-QuAL passed the functionality test against PVT variations and can perform well against the power supply scaling (from 1.8V to 0.5V). It also exhibits the least value of %NED and %NSD against PVT variations and when the power supply is scaled down compared to EE-SPFAL and SPGAL. At lower technology, WCS-QuAL, shows more improvement in energy dissipation than EE-SPFAL

VHDL-based Modelling Approach for the Digital Simulation of 4-phase Adiabatic Logic Design

In comparison to conventional CMOS (non-adiabatic logic), the verification of the functionality and the low energy traits of adiabatic logic techniques are generally performed using transient simulations at the transistor level. However, as the size and complexity of the adiabatic system increases, the amount of time required to design and simulate also increases. Moreover, due to the complexity of synchronizing the power-clock phases, debugging of errors becomes difficult too thus, increasing the overall verification time. This paper proposes a VHSIC Hardware Descriptive Language (VHDL) based modelling approach for developing models representing the 4-phase adiabatic logic designs. Using the proposed approach, the functional errors can be detected and corrected at an early design stage so that when designing adiabatic circuits at the transistor level, the circuit performs correctly and the time for debugging the errors can substantially be reduced. The function defining the four periods of the trapezoidal AC power-clock is defined in a package which is followed by designing a library containing the behavioral VHDL models of adiabatic logic gates namely; AND/NAND, OR/NOR and XOR/XNOR. Finally, the model library is used to develop and verify the structural VHDL representation of the 4-phase 2-bit ring-counter and 3-bit up-down counter, as a design example that demonstrates the practicality of the proposed approach

Investigation of Stepwise Charging Circuits for Power-Clock Generation in Adiabatic Logic

The generation of power-clocks in adiabatic integrated circuits is investigated. Specifically, we consider stepwise charging strategies (2, 3, 4, 5, 6, 7, and 8-step) based on tank-capacitor circuits, comparing them in terms of their energy recovery properties and complexity. We show that energy recovery achievable depends on the tank-capacitor size. We also show that tank-capacitor sizes can be reduced as their number increases concluding that combined tank capacitance (CTT) versus load capacitance (CL) ratio is the significant parameter. We propose that using a CTT/CL ratio of 10 and using a 4-step charging power-clock constitute appropriate trade-offs in practical circuits