Circuit Level Techniques for Power and Reliability Optimization of CMOS Logic

Technology scaling trends lead to shrinking of the individual elements like transistors and wires in digital systems. The main driving force behind this is cutting the cost of the systems while the systems are filled with extra functionalities. This is the reason why a 3 GHz Intel processor now is priced less than what a 50MHz processor was priced 10 years ago. As in most cases, this comes with a price. This price is the complex design process and problems that stem from the reduction in physical dimensions. As the transistors became smaller in size and the systems became faster, issues like power consumption, signal integrity, soft error tolerance, and testing became serious challenges. There is an increasing demand to put CAD tools in the design flow to address these issues at every step of the design process. First part of this research investigates circuit level techniques to reduce power consumption in digital systems. In second part, improving soft error tolerance of digital systems is considered as a trade off problem between power and reliability and a power aware dynamic soft error tolerance control strategy is developed. The objective of this research is to provide CAD tools and circuit design techniques to optimize power consumption and to increase soft error tolerance of digital circuits. Multiple supply and threshold voltages are used to reduce power consumption. Variable supply and threshold voltages are used together with variable capacitances to develop a dynamic soft error tolerance control scheme.Ph.D.Committee Chair: Abhijit Chatterjee; Committee Member: Adit D. Singh; Committee Member: Hsien-Hsin S. Lee; Committee Member: Madhavan Swaminathan; Committee Member: Vijay K. Madisett

The elusive metric for low-power architecture research

The Energy-Delay product or ED product was proposed as a metric to gauge design effectiveness. This metric is widely used in the area of low-power architecture research, however it is also often improperly used when reporting a new architecture design that addresses energy-performance effectiveness. In this paper, we discuss two common fallacies from the literature: (1) the way the ED product is calculated, and (2) issues of introducing additional hardware structures to reduce dynamic switching activities. When using the ED product without meticulous consideration, a seemingly energy-efficient design could turn out to be a more energy-consuming one. 1

Algorithm for achieving minimum energy consumption in CMOS circuits using multiple supply and threshold voltages at the module level

This paper proposes an optimum methodology for assigning supply and threshold voltages to modules in a CMOS circuit such that the overall energy consumption is minimized for a given delay constraint. The modules of the circuit should have large enough gate depths such that the delay and energy penalties of the level shifters connecting them are negligible. Both static and dynamic energy are considered in the optimization. Energy savings of up to 48 % have been achieved on various example circuits. The first step in the optimization finds optimum supply and threshold voltages for each module in the circuit. If the circuit has a large number of modules, this step might yield a correspondingly large number of different supply and threshold voltages for minimum energy consumption. Since having a large number of different supply and threshold voltages on an IC is not feasible in current technologies, an additional step clusters the multiple voltages obtained from the first step into a fixed number of supply and threshold voltages (for example, 2 different supply voltages and 2 different threshold voltages). In addition to the application of this method to circuit optimization, it can also be applied to a wide range of problems with delay constraints, such as software tasks running on a dynamically variable VDD and Vth processor. 1

CAD Tools and Algorithms

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