Mobile Vision-based Automatic Counting of Bacteria Colonies

The procedure for counting colonies is often performed manually and the process is lengthy and tedious. For that reason, several methods that rely on digital images for automatically counting cells and bacteria colonies have been proposed. Fully automated and high throughput hardware imaging instruments are also available, but such machines are extremely costly. In this paper, we introduce a mobile based computer vision algorithm for automatic bacteria colony counting using morphological operations and transforms in image processing, on a custom Android mobile cross-platform open source software and written in Java, C++ and Open CV computer vision library. The results have shown are promising given that the acquisition and detection were done in a noncontrolled environment

Modelling of overlay virtual metrology system in photolithography process

Prior works on overlay VM system applied wafer-level modelling approach by utilizing fault detection and classification (FDC) data from the photolithography equipment as the source data to construct process representatives for each wafer. However, owing to active research for continuous improvement, FDC system may be taken offline for enhancement works. When FDC system undergoes these activities, FDC-based VM system would be rendered inefficacious as FDC data would not be available. Hence, during such events, a non-FDC based VM system with sufficient competency is required to sustain the production line until the FDC-based VM system is able to resume service. Motivated by a real-world production environment of a 200mm semiconductor manufacturing plant (fab), this work aims to realise a non-FDC based overlay VM system to sustain the production line when FDC system undergoes offline activities. Realizing non-FDC based system is a non-trivial task. Without the availability of the FDC system, process data can only be sampled at low frequency, and only an averaged reading per sensor is available for each wafer’s fabrication process from the fabrication equipment. This limitation resulted in process data that have low process characteristic depiction capability and thus, decreases the prediction capability of the data mining algorithms for a competent VM system. Hence, a different VM modelling approach is required to realise a competent VM system. By using a different modelling paradigm, this work proposes a lot-level modelling approach to realise the non-FDC based overlay VM. Next, this work proposes a joint prediction modelling approach to create the prediction system of the VM. The joint prediction model first performs a classification task to identify wafer lots with faulty wafers. Using the proposed modelling, a smart sampling system termed C2O is realised in this work. The experimental results showed that using the proposed approaches, C2O is capable to achieve a true positive rate (TPR) of 71.34% for the classification task and mean absolute scaled error (MASE) of 8.48 for the regression task

Virtual Metrology in Semiconductor Fabrication Foundry Using Deep Learning Neural Networks

Physical metrology inspections are crucial in semiconductor fabrication foundry to ensure wafers are fabricated within the production specification limits and prevent faulty wafers from being shipped and installed in customers’ devices. However, it is not possible to examine every wafer as such inspection would incur impractical cost on manpower, finances, and production cycle time (CT) of fabrication foundries (fabs). Virtual metrology (VM) presents an alternate approach to perform metrology inspection without incurring high costs by using machine learning (ML) models. By leveraging historical equipment and process data, ML models can be calibrated to estimate the targeted metrology variables to estimate the quality of wafers, thereby performing virtual inspection on wafers. Recently, VM researchers begin introducing deep learning (DL) into VM research works to examine its capability. Specifically, the VM researchers experimented on the convolutional neural network (CNN). The targeted metrologies are metrologies of plasma-based processes in both etching and chemical vapor deposition. Initial success has been reported by the VM researchers. While various CNN-based VM models have been proposed plasma-based fabrication processes, it has yet to be experimented in photolithography process. Motivated by the initial successes of CNN in plasma-based processes, this work is an initiative to experiment CNN’s performance in predicting the overlay errors of photolithography process. Using data from a real fab, this work first establishes a baseline using the methodology of a prior work. Then, the prediction results of the proposed CNN model are compared with the baseline. The results showed that CNN is able to further reduce the prediction errors

Incoming Work-In-Progress Prediction in Semiconductor Fabrication Foundry Using Long Short-Term Memory

Preventive maintenance activities require a tool to be offline for long hour in order to perform the prescribed maintenance activities. Although preventive maintenance is crucial to ensure operational reliability and efficiency of the tool, long hour of preventive maintenance activities increases the cycle time of the semiconductor fabrication foundry (Fab). Therefore, this activity is usually performed when the incoming Work-in-Progress to the equipment is forecasted to be low. The current statistical forecasting approach has low accuracy because it lacks the ability to capture the time-dependent behavior of the Work-in-Progress. In this paper, we present a forecasting model that utilizes machine learning method to forecast the incoming Work-In-Progress. Specifically, our proposed model uses LSTM to forecast multistep ahead incoming Work-in-Progress prediction to an equipment group. The proposed model's prediction results were compared with the results of the current statistical forecasting method of the Fab. The experimental results demonstrated that the proposed model performed better than the statistical forecasting method in both hit rate and Pearson’s correlation coefficient, r

A Realizable Overlay Virtual Metrology System in Semiconductor Manufacturing: Proposal, Challenges and Future Perspective

Integrated circuits (IC) are fabricated on a wafer through stacked layers of circuit patterns. To ensure proper functionality, the overlay of each pattern layer must be within the tolerance. Inspecting each wafer’s overlay is unrealistic and impractical. Hence, wafers are selectively inspected at metrology stations through sampling strategies. With virtual metrology (VM), the metrology quality of the uninspected wafers can be estimated. Motivated by a real-world production environment of a 200mm semiconductor manufacturing plant (fab), a VM to estimate the overlay of the photolithography process is envisioned. Past researches on overlay VM leveraged fault detection and classification (FDC) data to estimate the overlay errors. As such, for fabs in the progress of completing their FDC development for photolithography equipment, a different modeling approach is required to realize an overlay VM that sustains the production line until FDC data can be leveraged for VM. With practical gaps that must be addressed in real fabs, this paper focuses on realizing an overlay VM for the photolithography process without leveraging FDC data. Therefore, the objectives of this paper are two folds: First, to identify the research challenges towards realizing the overlay VM. Second, to propose the future research perspectives of the envisioned overlay VM. Based on the future research perspectives, a two-steps overlay VM modeling approach utilizing data mining techniques is proposed toward realizing the envisioned overlay VM system. The proposed approach first classifies the process stability at the wafer lot level, and subsequently, performs overlay error estimations for wafers in the wafer lots classified with stable process. Linear regression models are proposed to perform overlay error estimations in this work to augment the interpretability of the overlay VM

The Implementation of a Smart Sampling Scheme C2O Utilizing Virtual Metrology in Semiconductor Manufacturing

Virtual metrology (VM) is an enabling technology capable of performing virtual inspection on the metrology quality of wafers. Instead of physically acquiring the metrology measurements, VM applies conjecture models on the process data of wafers to estimate the measurements of the targeted metrology variables. Prior works on overlay VM system utilized fault detection and classification (FDC) data as the process data for the conjecture models. Hence, when FDC data are unavailable owing to FDC system enhancement works, FDC-based VM models would be rendered inefficacious. During such events, a competent VM system using a different modeling approach is required to sustain the production line until FDC data resumes availability and FDC-based VM reaches production state. Motivated by a real-world production environment of a 200mm semiconductor manufacturing plant (fab), a novel wafer lot-level modeling approach for overlay VM was proposed in our prior work. Using the proposed modeling, a smart sampling scheme was also designed in the same work. The smart sampling scheme consists of two conjecture tasks, with the first task classifies the overlay quality of the wafers, and the second task estimates the overlay errors of the wafers classified with normal overlay quality. The abnormal ones are diverted to the physical metrology station. In this paper, the implementation of a smart sampling system, C2O, using the designed scheme and its experimental results are presented. The experimental results showed that C2O is capable to achieve a true positive rate (TPR) of 71.34% for the classification task and mean absolute scaled error (MASE) of 9.59 for the regression task. The obtained results set the baseline to measure the efficacy of future enhancement works, which have been enlisted and underway to augment the performance of the system so that its competency meets the requirements of real fab