Three-level stencil alignment fabrication of a high-k gate stack organic thin film transistor

In this work a high-k double-gate pentacene field-effect transistor architecture is presented. The devices are fabricated on a flexible polyimide substrate by three aligned levels of stencil lithography combined with standard photolithography. ALD-deposited high-k HfO2 and parylene D device passivation, together with Pt top-gate deposition provide very good electrostatic control of the channel, showing low leakage current and improved subthreshold. The ION/IOFF ratio is of the order of 106 and the IOFF lower than 0.1 pA/μm. We also report a comparison of the normal, FET-like (VD 0) modes of the p-OFET. We find a higher current drive in the reverse diode-like mode compared to normal FET-like mode. The reverse mode has clearly defined OFF and ON states versus the drain voltage and non-saturated output characteristics, which makes it suitable for the use in RF and analog applications of OFETs

Resonant-Body Fin-FETs with sub-nW power consumption

This paper presents, for the first time, experimental evidence on resonant-body Fin-FETs (RB-FinFET) with two independent lateral gates, operated from weak to strong inversion, which enables unique trade-off between power consumption and gain. Resonance frequencies from 25 MHz to 80 MHz with quality factors of the order of 3000 and motional resistances of the order of tens of kOhm are demonstrated with a mixer mode measurement technique, dedicated to ultra-scaled resonators. The power consumption of the active resonators can be reduced in weak inversion of the RB-FinFET well below 1nW, which is a record value compared to any prior active NEM resonator

Organic Thin Film Transistors on Flexible Polyimide Substrates Fabricated by Full Wafer Stencil Lithography

This paper presents new results on miniaturized organic thin film transistors (TFT) fabricated on a spin coated polyimide (PI) film. Patterning steps, that are vital for the integrity and electrical performances of the organic TFT, were performed using resistless shadow-mask lithography with two high precision MEMS fabricated stencils, thus avoiding solvents and high temperature processes. Both pentacene and source-drain (S/D) electrodes were directly patterned through stencils with high accuracy on wafer scale. The TFT have been characterized before and after peeling the flexible PI film off the rigid surface, showing full transistor functionality in both cases

Double-gate pentacene thin-film transistor with improved control in sub-threshold region

In this work double-gate pentacene TFT architecture is proposed and experimentally investigated. The devices are fabricated on a polyimide substrate based on a process that combines three levels of stencil lithography with standard photolithography. Similarly to the operation of a conventional double-gate silicon FET, the top-gate bias modulates the threshold voltage of the bottom-gate transistor and significantly improves the transistor sub-threshold swing and leakage current. Moreover, the double gate TFT shows good promise for the enhancement of I-ON/I-OFF, especially by the control of I-OFF in devices with poor top interfaces. (C) 2010 Elsevier Ltd. All rights reserved

Conception et caractérisation de microsystèmes électromécaniques (étude et fiabilité des capacités accordables des MEMS RF)

Les microsystèmes électromécaniques radiofréquence (MEMS RF) sont devenus ces dernières années des composants très prometteurs pour l amélioration des performances des circuits hyperfréquences. La possibilité de les intégrer avec des dispositifs classiques CMOS est aussi un avantage décisif. Par contre, la fiabilité des composants MEMS RF constitue le problème le plus important qui empêche souvent leur industrialisation. Dans ce mémoire une étude du fonctionnement des composants MEMS RF capacitifs est effectuée. Nous présentons la technologie compatible CMOS adoptée pour leur réalisation et les problèmes de fiabilité liés à cette technologie. Les outils de caractérisation spécifiques à l étude de la fiabilité sont décrits. Nous proposons une modélisation analytique du comportement électromécanique qui est comparée aux analyses par éléments finis des modèles 3D des MEMS RF capacitifs. Les tests électriques des capacités accordables ont révélé divers problèmes de fiabilité, telle qu une dépendance temporelle des caractéristiques électro-mécaniques et une forte sensibilité à la température. Le rôle de l environnement de mesure et les difficultés qui en résultent sur l interprétation des résultats expérimentaux sont également mise en évidence.GRENOBLE1-BU Sciences (384212103) / SudocGRENOBLE INP-Phelma (381852301) / SudocSudocFranceF

Fil chaud dans une microcavité et capteur de pression en technologie MEMS

National audienceIn this paper we present a new technology for wall shear stress integrated sensor fabrication. Thanks to the use of appropriate SOI wafers and wafer bonding technique, we found out an innovative technology that provides ultraminiaturized array-sensors needed in numerous microfluidic applications

Integration of MOSFET transistors in MEMS resonators for improved output detection

Micro-electromechanical (MEM) laterally vibrating square resonators and beams, fabricated via a prototyping technology combining FIB-micromachined gaps with conventional UV lithography in 1.35 mu m thick SOI are presented. Resonators with both capacitive and MOSFET detection and gaps of similar to 100 nm are demonstrated. Resonance frequencies of 32 MHz and 13 MHz were measured for squares and beams, respectively. The square shaped resonators have Q-factors in the order of 4000. This paper reports on a vibrating body MOS transistor active detection scheme integrated in a MEMS fabrication process to improve the signal read out