Automatic dynamic stabilization and correction of feedback amplifiers. II. Synthesis of correcting dipoles

This paper is the second part of the description of a novel stabilization algorithm suitable for feedback amplifiers. It deals with the effectiveness check of the proposed corrections. This test is based on return difference computations and gives limit values and nature determination for the correcting dipole. Optimization is introduced for improving the final characteristics. Two classical feedback amplifiers are analyzed and improved.Anglai

Automatic dynamic stabilization and correction of feedback amplifiers. I. Stability analysis

This paper is the description of a novel stabilization algorithm suitable for feedback amplifiers. It details how the stability test of the proposed structure may be reduced to a very simple check, easily implemented in a classical linear analysis program.Anglai

Boolean Mapping based on Testing Techniques

A novel approach to the Boolean mapping problem is presented. It relies on a Boolean matching algorithm based on testing techniques. The matching is detected by checking the controllability and observabilityofsignals in the cell structure against the subject functions of the network. The method was implemented inside the SIS [Tou90] synthesis environment. The comparison with the SIS structural mapping shows that the Boolean mapping achieve better results in similar or smaller computing time

Rapid Gate Matching with Don't Cares

Ending the logic synthesis, the technology mapping step maps the Boolean function on physical cells. This itep is based on a matching check, which complexity depends on the number of library cell inputs, and increases if don't cares are considered. The method presented here is based on fault analysis. Using a structural equivalent of the cell, it allows to prune dramatically the design space, and derives at the same time the input phase. The experimental results show a real improvement in CPU time compared to ROBDD based Boolean matching, and are promising to handle complex cells. 1 Introduction The technology mapping is the last and decisive step in the logic synthesis. After a technology independent minimization, the optimized multi-level logic network is splitted into simpler subfunctions (decomposition). The mapping then tries to cover the network by implementing one or more nodes with one or more cells from the target library, while trying to reduce area, delay, power, ... During..

The Controlling Value Boolean Matching

We present here the Controlling Value Boolean Matching based on fault analysis. The problem is to match a Boolean function with don't cares on library cells under arbitrary input permutations and/or input-output phase assignments. Most of the library cells can be represented by tree structure circuits. The approach presented here is suitable for these structures and computes the Boolean matching better than the structural matching used in SIS. It can handle library cells with a general topology and reconvergent paths. The benchmark test shows that the Controlling Value Boolean Matching can be as faster as the structural matching used in SIS

A new logic minimization method for multiplexor-based FPGA synthesis

A new method was presented for the minimization of incompletely specified functions using MBDs (modified binary decision diagrams: ROBDDs with a don't care terminal). The cost function to be minimized is the MBD size, which is an important factor in the case of FPGA synthesis. The method developed is based on a subgraph matching target to reduce the number of nodes of a MBD. The matching relies on the presence of a third terminal value X (don't care) in the MBD in order to represent an incompletely specified function in a single graph. The authors have compared the new method with ESPRESSO with respect to MBD size reduction and multiplexor based synthesis. The results obtained empirically confirm the initial hypothesis that two-level minimization techniques are inadequate for this purpose, and also show the efficiency of the proposed algorithm.Anglai