Rapid Gate Matching with Don't Cares

Abstract

Ending the logic synthesis, the technology mapping step maps the Boolean function on physical cells. This itep is based on a matching check, which complexity depends on the number of library cell inputs, and increases if don't cares are considered. The method presented here is based on fault analysis. Using a structural equivalent of the cell, it allows to prune dramatically the design space, and derives at the same time the input phase. The experimental results show a real improvement in CPU time compared to ROBDD based Boolean matching, and are promising to handle complex cells. 1 Introduction The technology mapping is the last and decisive step in the logic synthesis. After a technology independent minimization, the optimized multi-level logic network is splitted into simpler subfunctions (decomposition). The mapping then tries to cover the network by implementing one or more nodes with one or more cells from the target library, while trying to reduce area, delay, power, ... During..