A Method for Fast Evaluation of Sharing Set Management Strategies in Cache Coherence Protocols

International audienceWith the emergence of manycore processors with potentially hundreds of processors in the embedded market, the scalability of cache coherence protocols is again at stake. One seemingly simple issue is the management of the set of sharers of a memory block, but with that many processors, it is a major bottleneck in terms of hardware resources. In this paper, we define a high level simulation method to evaluate sharing set management strategies, using memory access traces obtained through cycle accurate simulation (e.g.gem5). The goal of the method is to rank protocols based on latency, traffic and hardware cost, to help either choose an existing approach for a given application context, or evaluate new approaches. We demonstrate the applicability of our proposal by evaluating three existing scalable cache coherence protocols, obtaining results consistent with previous, low level, evaluations much more rapidly

Trace-driven exploration of sharing set management strategies for cache coherence in manycores

International audienceDoing early design space exploration for manycore architectures is a challenge, all the more when the focus is on complex coherence protocols. Implementing such protocols in realistic simulation models is costly both in modelling effort and execution time. We propose a trace-driven method to accurately compare cache coherence protocols while keeping cache modelling at a high level of abstraction. We show what kind of design space exploration can be performed on an existing sharing set implementation proposal, the linked list sharing set management. By doing so, we demonstrate that our approach, while being still fairly accurate, is much easier to develop and much faster to execute than state of the art low level simulators

ExaNoDe: Combined Integration of Chiplets on Active Interposer with Bare Dice in a Multi-Chip-Module for Heterogeneous and Scalable High Performance Compute Nodes

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Active Interposer Technology for Chiplet-Based Advanced 3D System Architectures

International audienceWe report the first successful technology integration of chiplets on an active silicon interposer, fully processed, packaged and tested. Benefits of chiplet-based architectures are discussed. Built up technology is presented and focused on 3D interconnects process and characterization. 3D packaging is presented up to the successful structural test and characterization of the demonstrator