A Wireless, Battery-Powered Probe Based on a Dual-Tier CMOS SPAD Array for Charged Particle Sensing

A compact probe for charged particle imaging, with potential applications in source activity mapping and radio-guided surgery was designed and tested. The development of this technology holds significant implications for medical imaging, offering healthcare professionals accurate and efficient tools for diagnoses and treatments. To fulfill the portability requirements of these applications, the probe was designed for battery operation and wireless communication with a PC. The core sensor is a dual-layer CMOS SPAD detector, fabricated using 150 nm technology, which uses overlapping cells to produce a coincidence signal and reduce the dark count rate (DCR). The sensor is managed and interfaced with a microcontroller, and custom firmware was developed to facilitate communication with the sensor. The performance of the probe was evaluated by characterizing the on-board SPAD detector in terms of the DCR, and the results were consistent with the characterization measurements taken on the same chip samples using a purposely developed benchtop setup

DCR and crosstalk characterization of a bi-layered 24 × 72 CMOS SPAD array for charged particle detection

This paper presents the results from the crosstalk and dark count rate (DCR) characterization of a 24 × 72 single photon avalanche diode (SPAD) array, fabricated in a 150 nm CMOS technology. The chip under test consists of a dual layer detection system developed in view of applications to charged particle tracking. A three step procedure, used for the crosstalk characterization, is presented. The crosstalk probability, taking place in 5 × 5 sub arrays built around noisy pixels, has been computed. Eventually, random telegraph signal (RTS) fluctuations in DCR, at different bias conditions, are briefly discussed

DCR and crosstalk characterization of a bi-layered 24 × 72 CMOS SPAD array for charged particle detection

This paper presents the results from the crosstalk and dark count rate (DCR) characterization of a 24 × 72 single photon avalanche diode (SPAD) array, fabricated in a 150 nm CMOS technology. The chip under test consists of a dual layer detection system developed in view of applications to charged particle tracking. A three step procedure, used for the crosstalk characterization, is presented. The crosstalk probability, taking place in 5 × 5 sub arrays built around noisy pixels, has been computed. Eventually, random telegraph signal (RTS) fluctuations in DCR, at different bias conditions, are briefly discussed

Layered CMOS SPADs for Low Noise Detection of Charged Particles

This paper reports the characterization of SPAD arrays fabricated in a 150 nm CMOS technology in view of applications to the detection of charged particles. The test vehicle contains SPADs with different active area and operated with different quenching techniques, either passive or active. The set of devices under test (DUTs) consists of single-tier chips, about 30 mm2 in area, with dual-tier structures where two chips are face-to-face bump bonded to each other. In the dual-layer structure obtained in this way, the coincidence signal between overlapping SPAD pairs is read out, with a beneficial impact on the dark count noise performance. The DUT characterization was mainly focused on studying the breakdown voltage in the single-layer arrays and the dark count rate (DCR), measured in different working conditions, in both the single- and the dual-layer structures. Comparison between the DCR performance of the two configurations clearly emphasizes the advantage of the coincidence readout architecture

DCR Performance in Neutron-Irradiated CMOS SPADs from 150- To 180-nm Technologies

Single-photon avalanche diodes (SPADs) fabricated using two different CMOS technologies were exposed to a neutron source up to a maximum fluence of $3 imes 10^{11},,1$ -MeV neutron equivalent cm-2. Significant changes in the dark count rate (DCR), with a strong dependence on the fluence and the device active area, were detected after irradiation. A model for the probability of DCR degradation, accounting for the source spectrum and the geometry of the device under test (DUT), was proposed and proved to be in good agreement with experimental data. The model may be helpful in performing worst-case analysis of SPAD-based detection systems under neutron irradiation

APiX, a two-tier avalanche pixel sensor for digital charged particle detection

In this paper we present a position-sensitive detector based on the vertical integration of pairs of aligned pixels operating in Geiger-mode regime and designed for charged particle detection. This novel device exploits the coincidence between two simultaneous avalanche events to discriminate between particle-triggered detections and dark counts. This concept allows to have a reduced material budget and low power consumption in spite of a high granularity and fast timing response. A proof-of-principle prototype was designed and fabricated in a 150 nm CMOS process and vertically integrated through bump bonding. This first demonstrator has been characterized and tested with a high energy particle beams at CERN SPS/PS facilities, in different configurations, featuring a reduction of the dark-count rate (DCR) at room temperature from ∼100 kHz/mm2 to about 24 Hz/mm2 a particle detection efficiency limited only by the geometric factor. The device radiation tolerance has been investigated, via irradiation of single tiers with 10 keV X-rays up to a dose of 1 Mrad (SiO2) and with neutrons up to a fluence of 1011 cm−2. A second prototype, addressing the goal to improve the present fill-factor, has been designed, manufactured and approaches now the characterization phase. Potential applications of this sensor include high spatial resolution tracking in high-energy experiments, radiation monitoring in space and radiation imaging in nuclear medicine. A small hand-held demonstrator is under construction for radio-guided surgery