Stabilization of negative capacitance in ferroelectric capacitors with and without a metal interlayer

The negative capacitance operation of a ferroelectric material is not only an intriguing material science topic, but also a property with important technological applications in nanoscale electron devices. Despite the growing interest for possible applications, the very existence of negative capacitance is still actively debated, even because experimental results for ferroelectric capacitors with or without a metal interlayer led to quite contradicting indications. Here we present a comprehensive analysis of the NC operation in ferroelectric capacitorsandprovidenewinsightsaboutthediscrepanciesobservedinexperiments. Our models duly account for the three-dimensional nature of the problem and show a good agreement with several aspects of recent experiments. Our results also demonstrate that traps at the ferroelectric-dielectric interface play an important role in the feasibility of a stable negative capacitance operation in ferroelectric capacitors

A review of selected topics in physics based modeling for tunnel field-effect transistors

The research field on tunnel-FETs (TFETs) has been rapidly developing in the last ten years, driven by the quest for a new electronic switch operating at a supply voltage well below 1 V and thus delivering substantial improvements in the energy efficiency of integrated circuits. This paper reviews several aspects related to physics based modeling in TFETs, and shows how the description of these transistors implies a remarkable innovation and poses new challenges compared to conventional MOSFETs. A hierarchy of numerical models exist for TFETs covering a wide range of predictive capabilities and computational complexities. We start by reviewing seminal contributions on direct and indirect band-to-band tunneling (BTBT) modeling in semiconductors, from which most TCAD models have been actually derived. Then we move to the features and limitations of TCAD models themselves and to the discussion of what we define non-self-consistent quantum models, where BTBT is computed with rigorous quantum-mechanical models starting from frozen potential profiles and closed-boundary Schr\uf6dinger equation problems. We will then address models that solve the open-boundary Schr\uf6dinger equation problem, based either on the non-equilibrium Green's function NEGF or on the quantum-transmitting-boundary formalism, and show how the computational burden of these models may vary in a wide range depending on the Hamiltonian employed in the calculations. A specific section is devoted to TFETs based on 2D crystals and van der Waals hetero-structures. The main goal of this paper is to provide the reader with an introduction to the most important physics based models for TFETs, and with a possible guidance to the wide and rapidly developing literature in this exciting research field

A review of selected topics in physics based modeling for tunnel field-effect transistors

The research field on tunnel-FETs (TFETs) has been rapidly developing in the last ten years, driven by the quest for a new electronic switch operating at a supply voltage well below 1 V and thus delivering substantial improvements in the energy efficiency of integrated circuits. This paper reviews several aspects related to physics based modeling in TFETs, and shows how the description of these transistors implies a remarkable innovation and poses new challenges compared to conventional MOSFETs. A hierarchy of numerical models exist for TFETs covering a wide range of predictive capabilities and computational complexities. We start by reviewing seminal contributions on direct and indirect band-to-band tunneling (BTBT) modeling in semiconductors, from which most TCAD models have been actually derived. Then we move to the features and limitations of TCAD models themselves and to the discussion of what we define non-self-consistent quantum models, where BTBT is computed with rigorous quantum-mechanical models starting from frozen potential profiles and closed-boundary Schr\uf6dinger equation problems. We will then address models that solve the open-boundary Schr\uf6dinger equation problem, based either on the non-equilibrium Green's function NEGF or on the quantum-transmitting-boundary formalism, and show how the computational burden of these models may vary in a wide range depending on the Hamiltonian employed in the calculations. A specific section is devoted to TFETs based on 2D crystals and van der Waals hetero-structures. The main goal of this paper is to provide the reader with an introduction to the most important physics based models for TFETs, and with a possible guidance to the wide and rapidly developing literature in this exciting research field

Ferroelectric Negative Capacitance Transistors as Beyond Tunnel-FETs, Steep-Slope Devices: a Modeling, Simulation and Design Study

The IoT is one of the most trending businesses of modern times and has already opened a new world of opportunities for academic and industrial research. The IoT concept relies on a huge number of heterogeneous smart devices (i.e. $things$) that can communicate autonomously over the Internet, and also on a solid infrastructure to support the immense amount of datas continuously exchanged. Projections on the future of the IoT suggest a number of connected devices amply overcoming 50 billion within ten years, and with a predicted cost in terms of electricity consumption of over the 20% of the world energy demand.par In this context, IoT needs to be energy efficient under several aspects: for example by reducing the power consumption of each node of the smart grid and in the big data centers, and even by developing advanced software tools to nimbly manage the fluxes of informations. For these reasons different branches of electronic engineering can contribute to solve the overall efficiency issue.par This thesis addresses the problem from a nano-electronic perspective, analyzing possible solutions to limit the power dissipation in digital integrated circuits (ICs), in particular at the transistor level. In fact, in the last twenty years different strategies have been proposed to limit energy consumption in ICs but, due to some physical limitations of conventional Complementary Metal-Oxide-Semiconductor (CMOS) technology, an effective solution is still missing.par The main avenue to lower power dissipation in ICs has been for years the reduction of supply voltage $V_{DD}$, according to a $Dennardian$ $scaling$, but for modern scaled devices this cannot be done anymore without encountering important drawbacks in terms of process, voltage and temperature (PVT) variability. This led to an era known as $Dark$ $Silicon$ age, where a substantial area of a chip is kept underclocked or underpowered to meet power constraints, thus meaning that the full potential performance cannot be exploited and a huge number of devices is wasted. This approach is clearly a palliative and becomes more and more inefficient at each technology node as the number of devices approximately doubles inside the chip, so that is has become important to improve the energy efficiency at transistor level.par To address the problem from a device perspective, we need to consider the two main contributions to the total enegy dissipation: the dynamic and the standby energy. The first contribution scales quadratically with $V_{DD}$, but at very low $V_{DD}$ the standby energy becomes the most critical contribution, which is related to the subthreshold-swing of the current-voltage relation: the steeper the characteristic is, the lower the leakage current. Unfortunately, the conventional CMOS technology has a limitation under this perspective due to the thermionic-emission transport mechanism that physically restricts the lowest possible swing.par The investigation of new device concepts that can overcome this limit is an active and challenging field of research for modern electronics, and two of the most interesting technologies in this sense are the $Tunnel$ $FET$ (TFET) and the $Negative$-$Capacitance$ transistor (NC-FET). In this thesis we focus on the promising NC-FET concept, which integrates $ferroelectric$ materials in the gate-stack to improve both the on- and the off-state performances of the transistor.par In this work we present an extensive study on the negative-capacitance feature in ferroelectrics, according to the Landau-Khalatnikov theory, and investigate several original designs for ferroelectric NC-FETs in order to reduce energy consumption in ICs. Moreover, a comparison against experiments is carried out in order to validate our results and in the last chapter the sensitivity of NC-FETs to temperature, process variations and interface defects are also examined.The IoT is one of the most trending businesses of modern times and has already opened a new world of opportunities for academic and industrial research. The IoT concept relies on a huge number of heterogeneous smart devices (i.e. $things$) that can communicate autonomously over the Internet, and also on a solid infrastructure to support the immense amount of datas continuously exchanged. Projections on the future of the IoT suggest a number of connected devices amply overcoming 50 billion within ten years, and with a predicted cost in terms of electricity consumption of over the 20% of the world energy demand.par In this context, IoT needs to be energy efficient under several aspects: for example by reducing the power consumption of each node of the smart grid and in the big data centers, and even by developing advanced software tools to nimbly manage the fluxes of informations. For these reasons different branches of electronic engineering can contribute to solve the overall efficiency issue.par This thesis addresses the problem from a nano-electronic perspective, analyzing possible solutions to limit the power dissipation in digital integrated circuits (ICs), in particular at the transistor level. In fact, in the last twenty years different strategies have been proposed to limit energy consumption in ICs but, due to some physical limitations of conventional Complementary Metal-Oxide-Semiconductor (CMOS) technology, an effective solution is still missing.par The main avenue to lower power dissipation in ICs has been for years the reduction of supply voltage $V_{DD}$, according to a $Dennardian$ $scaling$, but for modern scaled devices this cannot be done anymore without encountering important drawbacks in terms of process, voltage and temperature (PVT) variability. This led to an era known as $Dark$ $Silicon$ age, where a substantial area of a chip is kept underclocked or underpowered to meet power constraints, thus meaning that the full potential performance cannot be exploited and a huge number of devices is wasted. This approach is clearly a palliative and becomes more and more inefficient at each technology node as the number of devices approximately doubles inside the chip, so that is has become important to improve the energy efficiency at transistor level.par To address the problem from a device perspective, we need to consider the two main contributions to the total enegy dissipation: the dynamic and the standby energy. The first contribution scales quadratically with $V_{DD}$, but at very low $V_{DD}$ the standby energy becomes the most critical contribution, which is related to the subthreshold-swing of the current-voltage relation: the steeper the characteristic is, the lower the leakage current. Unfortunately, the conventional CMOS technology has a limitation under this perspective due to the thermionic-emission transport mechanism that physically restricts the lowest possible swing.par The investigation of new device concepts that can overcome this limit is an active and challenging field of research for modern electronics, and two of the most interesting technologies in this sense are the $Tunnel$ $FET$ (TFET) and the $Negative$-$Capacitance$ transistor (NC-FET). In this thesis we focus on the promising NC-FET concept, which integrates $ferroelectric$ materials in the gate-stack to improve both the on- and the off-state performances of the transistor.par In this work we present an extensive study on the negative-capacitance feature in ferroelectrics, according to the Landau-Khalatnikov theory, and investigate several original designs for ferroelectric NC-FETs in order to reduce energy consumption in ICs. Moreover, a comparison against experiments is carried out in order to validate our results and in the last chapter the sensitivity of NC-FETs to temperature, process variations and interface defects are also examined

Energy minimization and Kirchhoff\u2019s laws in Negative Capacitance Ferroelectric Capacitors and MOSFETs

Capacitor networks consisting of ferroelectric and non ferroelectric materials can be described using two different perspectives: either the Gibb\u2019s energy minimization of the overall system, or the energy minimization of the ferroelectric capacitor alone, followed by Kirchhoff\u2019s laws used to connect the individual capacitors. This paper revisits the physics behind the networks of ferroelectric and non ferroelectric capacitors, and it helps reconcile the two above perspectives and the corresponding modelling methodologies

Supersteep Retrograde Doping in Ferroelectric MOSFETs for sub-60mV/dec Subthreshold Swing

We present a simulation study addressing the physics and design of ferroelectric MOSFETs and, in particular, we argue that a retrograde channel doping profile may help obtain a subthreshold swing well below 60mV/dec. Our analysis suggests that ferroelectric MOSFETs should be operated at gate voltages smaller than those triggering the hysteretic behavior, and have the potential to realize on current to off current ratios of 106 with a voltage swing as small as 0.2V , which is the ultimate goal for small slope transistors

Influence of interface traps on ferroelectric NC-FETs

In this letter, we present an intuitive theoretical framework to investigate the influence of interface traps in NC-FETs, operated either as steep-slope or as g m -boosted devices. Our analysis, validated by numerical simulations, shows that the sub-threshold swing can be either improved or degraded by the presence of defects, and that the threshold voltage can be reduced or increased depending on the design of the NC-FET

Tunnel FETsfor Ultra-Low Voltage Digital VLSI Circuits: Part I - Device-Circuit Interaction and Evaluation at Device Level

5his paper and the companion work present the results of a comparative study between the tunnel-FETs (TFETs) and conventional MOSFETs for ultralow power digital circuits targeting a V-DD below 500 mV. For this purpose, we employed numerical TCAD simulations, as well as mixed device-circuit and lookup-table simulations using either the SENTAURUS or the Verilog-A environment. In particular, in this paper, we explore the device circuit interaction in n- and p-type TFETs, and propose a design leading to a good tradeoff between the current leakage and transistor imbalance at ultralow V-DD, as required in ultralow voltage systems. Then, we systematically compare the I-OFF, I-ON, effective capacitance, OFF-state and ON-state stacking factors for TFETs, SOI, and bulk MOSFETs in a wide range of V-DD. These results allow us to infer preliminary indications about the amenability for an aggressive voltage scaling of TFETs compared with MOSFETs, which will be further developed in the companion paper. We also report simulation results for the sensitivity of the transistors to the variation of some key device parameters. Even these process variation results set the stage for a more thorough investigation addressed in the companion paper about the limits imposed by process variability to voltage scaling for either TFETs or MOSFETs circuits.reservedmixedD.Esseni; M.Guglielmini; B.Kapidani; T.Rollo; M.AliotoEsseni, David; M., Guglielmini; Kapidani, Bernard; Rollo, Tommaso; M., Aliot

Spinal Direct Current Stimulation Modulates Short Intracortical Inhibition

Objective Transcutaneous spinal direct current stimulation (tsDCS) is a new and safe technique for modulating spinal cord excitability. We assessed changes in intracortical excitability following tsDCS by evaluating changes in cortical silent period (cSP), paired-pulse short intracortical inhibition (SICI), and intracortical facilitation (ICF). Materials and Methods Healthy subjects were studied before (T0) and at different intervals (T1 and T2) after anodal, cathodal, and sham tsDCS (20', 2.0 mA) applied over the thoracic spinal cord (T10-T12). We assessed changes in cSP, SICI (interstimulus interval, ISI = 3 ms) and ICF (ISI = 10 ms). Motor-evoked potentials (MEPs) were recorded from first digital interosseus (FDI) and tibialis anterior (TA) muscles. Results Cathodal tsDCS increased MEP amplitudes at interstimulus interval of 3 ms, while anodal one elicited opposite effects (FDI: p = 0.0023; TA: p = 0.0004); conversely, tsDCS left MEP amplitudes unchanged at ISI of 10 ms (FDI: p = 0.39; TA: p = 0.45). No significant change in cSP duration was found from upper limb (p = 0.81) and lower limb (p = 0.33). Conclusion tsDCS modulates inhibitory GABA(A)ergic drive, as assessed by SICI, without interfering with cSP and ICF. The possibility to interfere with cortical processing makes tsDCS a useful approach to modulate spinal drive through nonspinal mechanisms. tsDCS could also represent an early rehabilitation strategy in patients with acute brain lesions, when other noninvasive brain stimulation (NIBS) tools are not indicated due to safety concerns, as well as in the treatment of spinal diseases or pain syndromes