Design Space Exploration Of Emerging Technologies For Energy Efficiency

As the demand for denser and faster electronics is growing, semiconductor industry has responded by aggressively scaling transistor sizes to several nanometers. Nano-scale devices provide higher density circuits while imposing crucial power, thermal and reliability problems to the system. As wire width continue to shrink, copper interconnects in high-performance systems will suffer from significant increase in resistivity due to surface roughness and grain boundary scattering resulting in electromigration issues. Furthermore, as technology scaling following Moore’s law is reaching its limits, 3D integration is a novel, promising and fast-emerging technology. 3D integration provides several advantages over 2D ICs by enabling, higher functionality, small form factor and heterogeneous implementation.The work presented in the HDR manuscript addresses the challenges of designing reliable and energy efficient circuits and systems for emerging technologies. It covers:-modeling and simulation for understanding the physical, electrical and thermal behavior on 3D integrated circuits.-physical design methods for power and signal integrity of 3D integrated circuits.-energy efficiency exploration on circuits based on carbon nanotube (CNT) interconnects

ClassONN:Classification with Oscillatory Neural Networks using the Kuramoto Model

Over the recent years, networks of coupled oscillators or oscillatory neural networks (ONNs) emerged as an alternative computing paradigm with information encoded in phase. Such networks are intrinsically attractive for associative memory applications such as pattern retrieval. Thus far, there are few works focusing on image classification using ONNs, as there is no straightforward way to do it. This paper investigates the performance of a neuromorphic phase-based classification model using a fully connected single layer ONNs. For benchmarking, we deploy the ONN on the full set of 28×28 binary MNIST handwritten digits and achieve around 70% accuracy on both training and test set. To the best of our knowledge, this is the first effort classifying such large images utilizing ONNs

ClassONN:Classification with Oscillatory Neural Networks using the Kuramoto Model

Over the recent years, networks of coupled oscillators or oscillatory neural networks (ONNs) emerged as an alternative computing paradigm with information encoded in phase. Such networks are intrinsically attractive for associative memory applications such as pattern retrieval. Thus far, there are few works focusing on image classification using ONNs, as there is no straightforward way to do it. This paper investigates the performance of a neuromorphic phase-based classification model using a fully connected single layer ONNs. For benchmarking, we deploy the ONN on the full set of 28×28 binary MNIST handwritten digits and achieve around 70% accuracy on both training and test set. To the best of our knowledge, this is the first effort classifying such large images utilizing ONNs

Ab Initio Simulations on the Structure and Properties of Supported Core-Shell Pt Nanoparticles on Single-Layer MoS₂

To effectively employ core-shell nanoparticles in catalysis and sensing necessarily requires a deep atomic-level understanding of their structural and electronic properties. Moreover, for both applications, nanoparticles are usually deposited over a support material which is known to lead to significant (and often unpredictable) changes in their properties and stability. In this work, we study a number of model Pt core-shell nanoparticles supported on single-layer molybdenum disulfide (MoS2). Our aim is to investigate the effect of the support on the properties of such nanoparticles, and we do so by means of first-principles simulations in the framework of density functional theory (DFT). Here, we show that the stability and the catalytic and/or sensing properties of the supported nanoparticles correlate with both strain and charge transfer, which are concurring and competing effects. Overall, our results suggest that core-shell Pt clusters supported on MoS2 may be successfully used in catalysis and in field-effect biosensing.</p

Pulse-level Noise Mitigation on Quantum Applications

Currently available quantum computers are prone to errors. Circuit optimization and error mitigation methods are needed to design quantum circuits to achieve better fidelity when executed on NISQ hardware. Dynamical decoupling (DD) is generally used to suppress the decoherence error and different DD strategies have been proposed. Moreover, the circuit fidelity can be improved by pulse-level optimization, such as creating hardware-native pulse-efficient gates. This paper implements all the popular DD sequences and evaluates their performances on IBM quantum chips with different characteristics for various well-known quantum applications. Also, we investigate combining DD with pulse-level optimization method and apply them to QAOA to solve Max-Cut problem. Based on the experimental results, we found that DD can be a benefit for only certain types of quantum algorithms, while the combination of DD and pulse-level optimization methods always has a positive impact. Finally, we provide several guidelines for users to learn how to use these pulse-level noise mitigation methods to build circuits for quantum applications with high fidelity

Oscillatory neural network learning for pattern recognition:an on-chip learning perspective and implementation

In the human brain, learning is continuous, while currently in AI, learning algorithms are pre-trained, making the model non-evolutive and predetermined. However, even in AI models, environment and input data change over time. Thus, there is a need to study continual learning algorithms. In particular, there is a need to investigate how to implement such continual learning algorithms on-chip. In this work, we focus on Oscillatory Neural Networks (ONNs), a neuromorphic computing paradigm performing auto-associative memory tasks, like Hopfield Neural Networks (HNNs). We study the adaptability of the HNN unsupervised learning rules to on-chip learning with ONN. In addition, we propose a first solution to implement unsupervised on-chip learning using a digital ONN design. We show that the architecture enables efficient ONN on-chip learning with Hebbian and Storkey learning rules in hundreds of microseconds for networks with up to 35 fully-connected digital oscillators.</p

qprof: a gprof-inspired quantum profiler

We introduce qprof, a new and extensible quantum program profiler able to generate profiling reports of various quantum circuits. We describe the internal structure and working of qprof and provide three practical examples on practical quantum circuits with increasing complexity. This tool will allow researchers to visualise their quantum implementation in a different way and reliably localise the bottlenecks for efficient code optimisation.Comment: 10 pages, 11 figure

Non-volatile resistive switching mechanism in single-layer MoS2 memristors:insights from ab initio modelling of Au and MoS2 interfaces

Non-volatile memristive devices based on two-dimensional (2D) layered materials provide an attractive alternative to conventional flash memory chips. Single-layer semiconductors, such as monolayer molybdenum disulphide (ML-MoS 2), enable the aggressive downscaling of devices towards greater system integration density. The "atomristor", the most compact device to date, has been shown to undergo a resistive switching between its high-resistance (HRS) and low-resistance (LRS) states of several orders of magnitude. The main hypothesis behind its working mechanism relies on the migration of sulphur vacancies in the proximity of the metal contact during device operation, thus inducing the variation of the Schottky barrier at the metal-semiconductor interface. However, the interface physics is not yet fully understood: other hypotheses were proposed, involving the migration of metal atoms from the electrode. In this work, we aim to elucidate the mechanism of the resistive switching in the atomristor. We carry out density functional theory (DFT) simulations on model Au and ML-MoS 2 interfaces with and without the presence of point defects, either vacancies or substitutions. To construct realistic interfaces, we combine DFT with Green's function surface simulations. Our findings reveal that it is not the mere presence of S vacancies but rather the migration of Au atoms from the electrode to MoS 2 that modulate the interface barrier. Indeed, Au atoms act as conductive "bridges", thus facilitating the flow of charge between the two materials. </p

Multi-qubit Dynamical Decoupling for Enhanced Crosstalk Suppression

Dynamical decoupling (DD) is one of the simplest error suppression methods, aiming to enhance the coherence of qubits in open quantum systems. Moreover, DD has demonstrated effectiveness in reducing coherent crosstalk, one major error source in near-term quantum hardware, which manifests from two types of interactions. Static crosstalk exists in various hardware platforms, including superconductor and semiconductor qubits, by virtue of always-on qubit-qubit coupling. Additionally, driven crosstalk may occur as an unwanted drive term due to leakage from driven gates on other qubits. Here we explore a novel staggered DD protocol tailored for multi-qubit systems that suppresses the decoherence error and both types of coherent crosstalk. We develop two experimental setups - an "idle-idle" experiment in which two pairs of qubits undergo free evolution simultaneously and a "driven-idle" experiment in which one pair is continuously driven during the free evolution of the other pair. These experiments are performed on an IBM Quantum superconducting processor and demonstrate the significant impact of the staggered DD protocol in suppressing both types of coherent crosstalk. When compared to the standard DD sequences from state-of-the-art methodologies with the application of X2 sequences, our staggered DD protocol enhances circuit fidelity by 19.7% and 8.5%, respectively, in addressing these two crosstalk types

A Hardware-Aware Heuristic for the Qubit Mapping Problem in the NISQ Era

Due to several physical limitations in the realisation of quantum hardware, today's quantum computers are qualified as Noisy Intermediate-Scale Quantum (NISQ) hardware. NISQ hardware is characterized by a small number of qubits (50 to a few hundred) and noisy operations. Moreover, current realisations of superconducting quantum chips do not have the ideal all-to-all connectivity between qubits but rather at most a nearest-neighbour connectivity. All these hardware restrictions add supplementary low-level requirements. They need to be addressed before submitting the quantum circuit to an actual chip. Satisfying these requirements is a tedious task for the programmer. Instead, the task of adapting the quantum circuit to a given hardware is left to the compiler. In this paper, we propose a Hardware-Aware mapping transition algorithm (HA) that takes the calibration data into account with the aim to improve the overall fidelity of the circuit. Evaluation results on IBM quantum hardware show that our HA approach can outperform the state of the art both in terms of the number of additional gates and circuit fidelity.Comment: IEEE Transactions on Quantum Engineering, 202