Leveraging Modern C++ in High-level Synthesis

High-level synthesis (HLS) enables automated conversion of high-level language algorithms into synthesizable register-transfer level code, allowing computation intensive algorithms to be accelerated on FPGAs. Most HLS tools have C++ as their input language, as it is widely known in both software and hardware industry. However, even though C++ receives a new standard every three years, the HLS tool vendors have mostly provided support and examples using C++98/03. Limiting to early C++ standards imposes a productivity penalty, since the newer standards provide both compilation time reductions and more concise, expressive, and maintainable way of writing code. In this study, we make the case for adopting modern C++ in HLS. We inspect the language features of C++11 and forward, and consider their benefits for HLS. We also test the present support for the modern language features with two state-of-the-art commercial HLS tools. Finally, we provide an extended example, demonstrating the increased clarity of code achieved using the newer standards. We note that the investigated HLS tools already have good support for modern C++ features, and urge their adoption to increase designer productivity.publishedVersionPeer reviewe

Framework for Creating Relevant, Accessible, and Adoptable KPI Models in an Industrial Setting

The development of software for modern products with lots of interfaces, layers and stakeholders has become very complex, increasing the risk of inefficiency. Key Performance Indicators (KPIs) can be used to identify bottlenecks and problems, but the challenge is how to create KPI models, processes and dashboards that help improving the development processes and can be adopted by all the stakeholders. We introduce the RelAA Framework - a bottom-up approach for monitoring product-focused software development. The RelAA (Relevant, Accessible and Adoptable) Framework is created in an industrial setup that currently includes around 350 persons in different phases of the software life cycle. The RelAA Framework is formed by analyzing existing KPIs and tools, gathering feedback from development teams, management, business representatives, and other stakeholders, and creating intuitive ways to share information related to KPIs. The RelAA Framework itself does not define exact KPIs for the organization to adopt, but it provides a process and model how to create, document and utilize KPIs. The RelAA Framework ensures relevance, accessibility, and adoption of KPIs across stakeholders and organization.acceptedVersionPeer reviewe

A Resilient System Design to Boot a RISC-V MPSoC

This paper presents a highly resilient boot process design for Ballast, a new RISC- V based multiprocessor system-on-chip (SoC). An open source RISC- V SoC was adapted as a bootstrap processor and customized to meet our requirement for guaranteed chip wake-up. We outline the characteristic challenges of implementing a large program into a read-only memory (ROM) used for booting and propose generally applica-ble workflows to verify the boot process for application specific integrated circuit (ASIC) synthesis. We implemented four distinct boot modes. Two modes that load a software bootloader autonomously from an SD card are implemented for a secure digital input output (SDIO) interface and for a serial peripheral interface (SPI), respectively. Another SDIO based mode allows for direct program execution from external memory, while the last mode is based on usage of a RISC- V debug module. The boot process was verified with instruction set simulation, register transfer level simulation, gate-level simulation and field-programmable gate array prototyping. We received the fabricated ASIC samples and were able to successfully boot the chip via all boot modes on our custom circuit board.Peer reviewe

Age of Information in a SWIPT and URLLC enabled Wireless Communications System

This paper estimates the freshness of the information in a wireless relay communication system that employs simultaneous wireless information and power transfer (SWIPT) operating under ultra-reliable low-latency communication (URLLC) constraints. The Age of Information (AoI) metric calculates the time difference between the current time and the timestamp of the most recent update received by the receiver is used here to estimate the freshness of information. The short packet communication scheme is used to fulfil the reliability and latency requirements of the proposed wireless network and its performance is analysed using finite block length theory. In addition, by utilising novel approximation approaches, expressions for the average AoI (AAoI) of the proposed system are derived. Finally, numerical analysis is used to evaluate and validate derived results

An Efficient High-level Synthesis Implementation of the MUSIC DoA Algorithm for FPGA

High-level synthesis (HLS) promises to increase the design and verification productivity for digital hardware systems. However, the industry still predominantly uses more time-consuming manual register-transfer level techniques instead of HLS. To accelerate the adoption of HLS, it is vital to explore if it is possible to achieve competitive results with this method. To that end, this paper demonstrates an HLS implementation of the well-known MUSIC algorithm for estimating the direction of arrival of a radio signal. We use as a receiver a four-antenna uniform linear array with one signal source and a resolution of one degree. For the computationally heavy eigenvalue decomposition within MUSIC, we employ the iterative Jacobi algorithm. We target two different Virtex FPGAs for synthesis and obtain results faring well in comparison to the previous literature, with 5.0 μs microseconds latency, high accuracy, and low resource consumption. The results show that HLS is suitable for implementing these kinds of algorithms on FPGA.Peer reviewe

Compact hardware design of Whirlpool hashing core

Weaknesses have recently been found in the widely used cryptographic hash functions SHA-1 and MD5. A potential alternative for these algorithms is the Whirlpool hash function, which has been standardized by ISO/IEC and evaluated in the European research project NESSIE. In this paper we present a Whirlpool hashing hardware core suited for devices in which low cost is desired. The core constitutes of a novel 8-bit architecture that allows compact realizations of the algorithm. In the Xilinx Virtex-II Pro XC2VP40 FPGA, our implementation consumes 376 slices and achieves the throughput of 81.5 Mbit/s. The resource utilization of our design is one fourth of the smallest Whirlpool implementation presented to date.

Review of Hardware Architectures for Advanced Encryption Standard Implementations Considering Wireless Sensor Networks

Abstract. Wireless Sensor Networks (WSN) are seen as attractive solutions for various monitoring and controlling applications, a large part of which require cryptographic protection. Due to the strict cost and power consumption requirements, their cryptographic implementations should be compact and energy-efficient. In this paper, we survey hardware architectures proposed for Advanced Encryption Standard (AES) implementations in low-cost and low-power devices. The survey considers both dedicated hardware and specialized processor designs. According to our review, currently 8-bit dedicated hardware designs seem to be the most feasible solutions for embedded, low-power WSN nodes. Alternatively, compact special functional units can be used for extending the instruction sets of WSN node processors for efficient AES execution.