VLSI Implementation of Cascaded Integrator Comb Filters for DSP Applications

The recursive comb filters or Cascaded Integrator Comb filter (CIC) are commonly used as decimators for the sigma delta modulators. This paper presents the VLSI implementation, analysis and design of high speed CIC filters which are based on a low-pass filter. These filters are used in the signal decimation which has the effect on reducing the sampling rate. It is also chosen because its attractive property of both low power and low complexity since it dose not required a multiplier. Simulink toolbox available in Matlab software which is used to simulator and Verilog HDL coding help to verify the functionality of the CIC filters. Design procedures and examples are given for CIC filter with emphasis on frequency response, transfer function and register width. The implementation results show using Modified Carry Look-ahead Adder for summation and also apply pipelined filter structure enhanced high speed and make it more compatible for DSP applications

High Resolution Single-Chip Radix II FFT Processor for High- Tech Application

Electrical motors are vital components of many industrial processes and their operation failure leads losing in production line. Motor functionality and its behavior should be monitored to avoid production failure catastrophe. Hence, a high‐tech DSP processor is a significant method for electrical harmonic analysis that can be realized as embedded systems. This chapter introduces principal embedded design of novel high‐tech 1024‐point FFT processor architecture for high performance harmonic measurement techniques. In FFT processor algorithm pipelining and parallel implementation are incorporated in order to enhance the performance. The proposed FFT makes use of floating point to realize higher precision FFT. Since floating‐point architecture limits the maximum clock frequency and increases the power consumption, the chapter focuses on improving the speed, area, resolution and power consumption, as well as latency for the FFT. It illustrates very large‐scale integration (VLSI) implementation of the floating‐point parallel pipelined (FPP) 1024‐point Radix II FFT processor with applying novel architecture that makes use of only single butterfly incorporation of intelligent controller. The functionality of the conventional Radix II FFT was verified as embedded in FPGA prototyping. For area and power consumption, the proposed Radix II FPP‐FFT was optimized in ASIC under Silterra 0.18 µm and Mimos 0.35 µm technology libraries