The recursive comb filters or Cascaded Integrator Comb filter (CIC) are commonly used as decimators for the sigma delta modulators. This paper presents the VLSI implementation, analysis and design of high speed CIC filters which are based on a low-pass filter. These filters are used in the signal decimation which has the effect on reducing the sampling rate. It is also chosen because its attractive property of both low power and low complexity since it dose not required a multiplier. Simulink toolbox available in Matlab software which is used to simulator and Verilog HDL coding help to verify the functionality of the CIC filters. Design procedures and examples are given for CIC filter with emphasis on frequency response, transfer function and register width. The implementation results show using Modified Carry Look-ahead Adder for summation and also apply pipelined filter structure enhanced high speed and make it more compatible for DSP applications

Othman, Masuri

Teymourzadeh, Rozita

English

Munich Personal RePEc Archive

MPRA
Munich Personal RePEc Archive
VLSI Implementation of Cascaded
Integrator Comb Filters for DSP
Applications
Rozita Teymourzadeh and Masuri Othman
UKM University
20. January 2006
Online at http://mpra.ub.uni-muenchen.de/41944/
MPRA Paper No. 41944, posted 16. October 2012 10:46 UTC
  
VLSI Implementation of Cascaded Integrator Comb 
Filters for DSP Applications 
 
 
Rozita Teymourzadeh , Masuri Othman 
 
Department of Electrical, Electronic and Systems Engineering 
VLSI Design Research Group 
National University of Malaysia 
rozita60@vlsi.eng.ukm.my  
 
Abstract 
 
The recursive comb filters or Cascaded Integrator 
Comb filter (CIC) are commonly used as decimators for 
the sigma delta modulators. This paper presents the 
VLSI implementation, analysis and design of high speed 
CIC filters which are based on a low-pass filter. These 
filters are used in the signal decimation which has the 
effect on reducing the sampling rate. It is also chosen 
because its attractive property of both low power and 
low complexity since it dose not required a multiplier. 
Simulink toolbox available in Matlab software which is 
used to simulator and Verilog HDL coding help to verify 
the functionality of the CIC filters. Design procedures 
and examples are given for CIC filter with emphasis on 
frequency response, transfer function and register width. 
The implementation results show using Modified Carry 
Look-ahead Adder for summation and also apply 
pipelined filter structure enhanced high speed and make 
it more compatible for DSP applications.   
 
Keyword: CIC, sigma delta, Decimation, Comb, 
recursive, truncation, MCLA. 
 
1 Introduction  
 
Electronic and communication system for speech  
 processing and radar make use of sigma delta modulator 
in their operation [1], [2]. Future systems are required to 
operate with high speed and therefore the sigma delta 
modulator must be designed accordingly. 
Sigma delta (∑Δ) modulator is an over sampled 
modulation technique which provides high resolution 
sample output in contrast to the standard Nyquist 
sampling technique. However at the output, the 
sampling process is needed in order to bring down the 
high sampling frequency and obtain high resolution. The 
CIC filter is a preferred technique for this purpose. In 
1981, Eugene Hogenauer [3] invented a new class of 
economical digital filter for decimation called a 
Cascaded Integrator Comb filter (CIC) or recursive 
comb filter. Additionally the CIC filter does not require 
storage for filter coefficients and multipliers as all 
coefficients are unity [4]. Furthermore its on-chip 
implementation is efficient because of its regular 
structure consisting of two basic building blocks, 
minimum external control and less complicated local 
timing is required and its change factors is 
reconfigurable with the addition of a scaling circuit and 
minimal changes to the filter timing. It is also used to 
perform filtering of the out of band quantization noise 
and prevent excess aliasing introduced during sampling 
rate decreasing. Hence enhanced high speed will be key 
issue in chip implementation of CIC decimators. This 
filter consists of three parts which are Integrator, comb 
and down sampler. CIC filter is considered as recursive 
filter because of the feedback loop in integrator circuit. 
The next section describes the mathematical formulation 
and block diagram of CIC filters in detail. Enhanced 
high speed architecture is explained in section 3. Section 
4 shows implementation and design result in brief. 
Finally conclusion is expressed in section 5. 
 
2 An overview of decimation system 
 
The purpose of the CIC filter is twofold; firstly to 
remove filtering noise which could be aliased back to 
the base band signals and secondly to convert high 
sample rate m-bit data stream at the output of the Sigma-
delta modulator to n-bit data stream with lower sample 
rate. This process is also known as decimation which is 
essentially performing the averaging and a rate reduction 
functions simultaneously. Figure 1 shows the decimation 
process using CIC filter.  
 
Fig.  1 Digital Decimation Process 
 
The two half band filters [7] are used to reduce remain 
sampling rate reduction to the Nyquist output rate. First 
half band filter and second half band filter make the 
frequency response more flat and sharp similar to ideal 
filter frequency response.  
Sigma delta 
modulator 
CIC filter 
Second 
half band 
filter 
First half 
band filter 
Droop 
correction
6.144 
MHz
384 
KHz
192 
KHz
96 
KHz
48 
KHz
Input 
Signal
21 R160 R 22 R 23 R
Droop correction filter is allocated to compensate pass 
band attenuation which is created by CIC filter. The 
frequency response of overall system will be shown in 
section 4.  
 
2.1 CIC filters structure 
 
The CIC filter consist of N stages of integrator and 
comb filter which are connected by a down sampler 
stage as shown in figure 1 in z domain. The CIC filter 
has the following transfer function: 
 










1
0
1
)(
)1(
)1(
)().()(
RM
k
Nk
N
NRM
N
C
N
I z
z
z
zHzHzH       (1) 
 
where N is the number of stage, M is the differential 
delay and R is the decimation factor.  
In this paper, N, M and R have been chosen to be 5, 1 
and 16 respectively to avoid overflow in each stages. 
 
R11
1
 z
RMz1SF R
FS
decimator CombIntegrator
Input 
sample rate
Output 
sample rate
 
 
Fig. 2 One-stage of CIC filter block diagram 
 
N, M and R are parameters to determine the register 
length requirements necessary to assure no data loss. 
Equation (1) can be express as follow: 
 
 
From the equation, the maximum register growth/width, 
maxG can be expressed as: 
  
                                 NRMG max                          (3) 
 
In other word, maxG  is the maximum register growth 
and a function of the maximum output magnitude due to 
the worst possible input conditions [3].  
If the input data word length is
inB , most significant bit 
(MSB) at the filter output, 
maxB is given by: 
                  ]1log[ 2max  inBRNB                 (4) 
 
In order to reduce the data loss, normally the first stage 
of the CIC filter has maximum number of bit compared 
to the other stages. Since the integrator stage works at 
the highest oversampling rate with a large internal word 
length, decimation ratio and filter order increase which 
result in more power consumption and speed limitation.  
 
2.2 Truncation for low power & high speed purpose 
 
Truncation means estimating and removing Least 
Significant Bit (LSB) to reduce the area requirements on 
chip and power consumption and also increase speed of 
calculation. Although this estimation and removing 
introduces additional error, the error can be made small 
enough to be acceptable for DSP applications. 
Figure 2 illustrates five stages of the CIC filter when 
maxB  is 25 bit so truncation is applied to reduce register 
width. Matlab software helps to find word length in 
integrator and comb section.  
 
1
Z
+
+
+
-
Integrator 1
25 bit
1
Z
+
+
Integrator 2
22 bit
R
1
Z
+
+
Integrator 3
20 bit
1
Z
+
+
Integrator 4
18 bit
1
Z
+
+
Integrator 5
16 bit
16
1
Z
Comb 1
16 bit
+
-
1
Z
Comb 2
16 bit
+
-
1
Z
Comb 3
16 bit
+
-
1
Z
Comb 4
16 bit
+
-
1
Z
Comb 5
16 bit
a_in
s_out
 
Fig. 3 Five-stages of truncated CIC filter include  
                                integrator and comb cell 
 
3 Speed Improvement  
 
There are two ways to speed up the CIC filter 
which describes as below. 
 
3.1 Pipeline structure 
 
One way to have high speed CIC filter is by 
implementing the pipeline filter structure. Figure 4 
shows pipeline CIC filter structure when truncation is 
also applied. In the pipelined structure, no additional 
pipeline registers are used. So that hardware requirement 
is the same as in the non-pipeline [6]. CIC decimation 
filter clock rate is determined by the first integrator stage 
that causes more propagation delay than any other stage 
due to maximum number of bit. So it is possible to use a 
higher clock rate for a CIC decimation filter if a pipeline 
structure is used in the integrator stages, as compared to 
non-pipelined integrator stages. Clock rate in integrator 
 N
N
RM
k
N
RM
k
k
N
RM
k
k
N
RM
k
k
NRM
k
k
RMz
zzzkhzH




































1
0
1
0
1
0
1
0
)1(
0
1
)()(
 
  (2) 
section is R times higher than in the comb section, so 
pipeline structure can not applied for comb section.  
 
1
Z
R
1
Z
1
Z
1
Z
1
Z
1
Z
1
Z
1
Z
1
Z
1
Z
+
+
+
-
+
+
+
+
+
+
+
+
+
-
+
- +-
+
-
25 bit 22 bit 20 bit 18 bit 16 bit
16
in
Comb 1
16 bit
Comb 2
16 bit
Comb 3
16 bit
Comb 4
16 bit
Comb 5
16 bit
out
Integrator 1 Integrator 2 Integrator 3 Integrator 4 Integrator 5
 
Fig. 4 Five-stage of truncated pipeline CIC filter  
                      include integrator and comb cell  
 
3.2 Modified Carry look-ahead Adder (MCLA) 
 
The other technique to increase speed is using 
Modified Carry Look-ahead Adder. The Carry Look-
ahead adder (CLA) is the fastest adder which can be 
used for speeding up purpose but the disadvantage of the 
CLA adder is that the carry logic is getting quite 
complicated for more than 4 bits so Modified Carry 
Look-ahead Adder (MCLA) is introduced to replace as 
adder. This improve in speed is due to the carry 
calculation in MCLA. In the ripple carry adder, most 
significant bit addition has to wait for the carry to ripple 
through from the least significant bit addition. Therefore 
the carry of MCLA adder has become a focus of study in 
speeding up the adder circuits [5]. The 8 bit MCLA 
structure is shown in Figure 6. Its block diagram 
consists of 2, 4-bit module which is connected and each 
previous 4 bit calculates carry out for the next carry. The 
CIC filter in this paper has five MCLA in integrator 
parts. The maximum number of bit is 25 and it is 
decreased in next stages. So it truncated respectively to 
25, 22, 20, 18 and 16 bit in each adder, left to right 
Notice that each 4-bit adder provides a group Propagate 
and Generate Signal, which is used by the MCLA Logic 
block. The group Propagate PG and Generate GG of a 4-
bit adder will have the following expressions:  
 
                        0123 ... ppppPG                              (5) 
0123123233 ...... gpppgppgpgGG          (6) 
 
The most important equations to obtain carry of each 
stage have been defined as below: 
 
                     ).( 0001 cpgc                                 (7) 
             )..().( 0010112 cppgpgc                    (8) 
 )..()..().( 0.0120121223 cpppgppgpgc   (9) 
)...()..().( 01231232334 gpppgppgpgc 
)....( 00123 cpppp 
 
Calculation of MCLA is based on above equations. 8-Bit 
MCLA Adder could be constructed continuing along in 
the same logic pattern, with the MSB carry-out resulting 
from OR & AND gates. 
The Verilog code has been written to implement 
summation. The MCLA Verilog code was downloaded 
to the Xilinx FPGA chip.  
It was found minimum clock period on FPGA board is 
4.389ns (Maximum Frequency is 220 MHz). 
 
a0b0
p0
g0
a1b1
p1g1
a2b2
p2
c1
c2
a3b3
p3g3
CLL-1
c3
a5b5
p5g5
a6b6
p6g6
c6
a7b7
p7g7
c7
a4b4
p4g4
c4c5
CLL-2
c8
c4
s0s1s2
g2
s3
PFAPFAPFA
s5s6s7 s4
PFA PFA PFAPFA
 
Fig. 5 The 8 bit MCLA structure 
 
4 Design Results 
 
Figure 6 illustrate the frequency response of the CIC 
filter when the sampling frequency is 6.144 MHz and 
the pass band frequency is 348 KHz. 
 
0 1 2 3 4 5 6 7
x 10
5
-160
-140
-120
-100
-80
-60
-40
-20
0
SINC Filter
Frequency(Hz)
A
m
p
li
tu
d
e
(d
B
)
 
   
Fig. 6 Comb filter frequency response for R=16, 
                                          M=1 and N=5 
(10) 
After the sigma delta modulator, the sampling rate must 
be reduced to 47 KHz which is the Nyquist sampling 
rate. This is carried out in 4-stages. The first stage 
involves the reduction of the sampling frequency by the 
decimation factor of 16. This is done by the CIC filter.  
The remaining 3 stages involve the reduction of the 
sampling frequency by the decimation factor of 2 only 
which are carried out by the first half band, droop 
correction and the second half band respectively. The 
Simulation results for all 4 stages are given in figure 7.     
  
 
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
x 10
5
-160
-140
-120
-100
-80
-60
-40
-20
0
First Half-band Filter
Frequency (Hz)
A
m
p
li
tu
d
e
(d
B
)
0 1 2 3 4 5 6 7 8 9 10
x 10
4
-160
-140
-120
-100
-80
-60
-40
-20
0
Droop Correction Filter
Frequency (Hz)
A
m
p
li
tu
d
e
(d
B
)
 
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
x 10
4
-160
-140
-120
-100
-80
-60
-40
-20
0
Second Half-band Filter
Frequency (Hz)
A
m
p
li
tu
d
e
(d
B
)
 
0 5 10 15 20 25 30 35 40 45 50
-160
-140
-120
-100
-80
-60
-40
-20
0
Overal System
Frequency (kHz)
A
m
p
li
tu
d
e
(d
B
)
 
 
Fig. 7  frequency response of (a) first half band filter (b) 
droop correction (c) second half band filter (d) overall 
decimation process , Over sampling ratio=128 
 
 
Figure 8 shows the measured baseband output 
spectra before (Figure 8(a)) and after (Figure 8(b)) the 
decimation functions.  
The CIC filter Verilog code was written and simulated 
by Matlab software. 
It is found Signal to Noise ratio (SNR) is 141.56 dB in 
sigma delta modulator output and SNR is increased to 
145.35 dB in the decimation stages. 
To improve the signal to noise ratio, word length of 
recursive CIC filter should be increased but the speed of 
filter calculation is also decreased.  
 
 
(a) 
(a) 
(b) 
(c) 
(d) 
 
(b) 
 
Fig. 8 Signal spectra (a) Output sigma delta modulator 
                       SNR (b) Output CIC filter SNR 
 
5 Conclusions 
 
Recursive CIC filters have been designed and 
investigated. Enhanced high Speed CIC filters was 
obtained by the pipeline structure and by using the 
modified carry look-ahead adder (MCLA). The 
evaluation indicates that the pipelined CIC filter with 
MCLA adder is attractive due to high speed when both 
the decimation ratio and filter order are not high as 
stated in the Hogenauer Comb filter.  Since the first 
stage of CIC filter require maximum word length and 
also because of the recursive loop in its structure, thus 
power is limited by the calculation in integrator stage, so 
the truncation will reduced the power consumption to 
obtain high speed operation.  
 
References 
[1] R.E.Crochiere and L.R. Rabiner, Multirate Digital 
Signal Processing, Engelwood Cliffs, Prentice 
Hall, New Jersey, 1983. 
[2] P.P. Vaidyanathan, Multirate Systems and Filter 
Banks, Engelwood Cliffs, Prentice Hall, New 
Jersey, 1993. 
[3] E.B. Hogenauer, An Economical Class of digital 
filters for Decimation and interpolation, IEEE 
Transactions on Acoustics, Speech, and Signal 
Prosessing, Vol. ASSP-29,pp.155-162, April 1981. 
[4] Sangil Park, Principles of Sigma-delta Modulation 
for Analog-to-Digital Converters, Motorola Inc, 
APR8/D Rev.1, 1990 
[5] Michael D. Ciletti, Advanced Digital design with 
the Verilog HDL, Prentice Hall, Department of 
Electrical and Computer Engineering University of 
Colorado at Colorado Springs, 2003  
[6] Y. Djadi and T. A. Kwasniewski, C. Chan and V. 
Szwarc, “A high throughput Programmable 
Decimation and Interpolation Filter”, Proceeding 
of International Conference on Signal Processing 
Applications and Technology, pp.1743-1748, 1994 
[7] Brian P. Brandt and Bruce A. Wooley, A Low-
Power, Area-Efficient Digital Filter for Decimation 
and Interpolation, IEEE Journal of Solid-State 
Circuits, Vol. 29, No.6, June 1994 


VLSI Implementation of Cascaded Integrator Comb Filters for DSP Applications

Munich RePEc Personal Archive

MPRAMunich Personal RePEc ArchiveVLSI Implementation of CascadedIntegrator Comb Filters for DSPApplicationsRozita Teymourzadeh and Masuri OthmanUKM University20. January 2006Online at http://mpra.ub.uni-muenchen.de/41944/MPRA Paper No. 41944, posted 16. October 2012 10:46 UTC  VLSI Implementation of Cascaded Integrator Comb Filters for DSP Applications   Rozita Teymourzadeh , Masuri Othman  Department of Electrical, Electronic and Systems Engineering VLSI Design Research Group National University of Malaysia rozita60@vlsi.eng.ukm.my   Abstract  The recursive comb filters or Cascaded Integrator Comb filter (CIC) are commonly used as decimators for the sigma delta modulators. This paper presents the VLSI implementation, analysis and design of high speed CIC filters which are based on a low-pass filter. These filters are used in the signal decimation which has the effect on reducing the sampling rate. It is also chosen because its attractive property of both low power and low complexity since it dose not required a multiplier. Simulink toolbox available in Matlab software which is used to simulator and Verilog HDL coding help to verify the functionality of the CIC filters. Design procedures and examples are given for CIC filter with emphasis on frequency response, transfer function and register width. The implementation results show using Modified Carry Look-ahead Adder for summation and also apply pipelined filter structure enhanced high speed and make it more compatible for DSP applications.    Keyword: CIC, sigma delta, Decimation, Comb, recursive, truncation, MCLA.  1 Introduction   Electronic and communication system for speech   processing and radar make use of sigma delta modulator in their operation [1], [2]. Future systems are required to operate with high speed and therefore the sigma delta modulator must be designed accordingly. Sigma delta (∑Δ) modulator is an over sampled modulation technique which provides high resolution sample output in contrast to the standard Nyquist sampling technique. However at the output, the sampling process is needed in order to bring down the high sampling frequency and obtain high resolution. The CIC filter is a preferred technique for this purpose. In 1981, Eugene Hogenauer [3] invented a new class of economical digital filter for decimation called a Cascaded Integrator Comb filter (CIC) or recursive comb filter. Additionally the CIC filter does not require storage for filter coefficients and multipliers as all coefficients are unity [4]. Furthermore its on-chip implementation is efficient because of its regular structure consisting of two basic building blocks, minimum external control and less complicated local timing is required and its change factors is reconfigurable with the addition of a scaling circuit and minimal changes to the filter timing. It is also used to perform filtering of the out of band quantization noise and prevent excess aliasing introduced during sampling rate decreasing. Hence enhanced high speed will be key issue in chip implementation of CIC decimators. This filter consists of three parts which are Integrator, comb and down sampler. CIC filter is considered as recursive filter because of the feedback loop in integrator circuit. The next section describes the mathematical formulation and block diagram of CIC filters in detail. Enhanced high speed architecture is explained in section 3. Section 4 shows implementation and design result in brief. Finally conclusion is expressed in section 5.  2 An overview of decimation system  The purpose of the CIC filter is twofold; firstly to remove filtering noise which could be aliased back to the base band signals and secondly to convert high sample rate m-bit data stream at the output of the Sigma-delta modulator to n-bit data stream with lower sample rate. This process is also known as decimation which is essentially performing the averaging and a rate reduction functions simultaneously. Figure 1 shows the decimation process using CIC filter.   Fig.  1 Digital Decimation Process  The two half band filters [7] are used to reduce remain sampling rate reduction to the Nyquist output rate. First half band filter and second half band filter make the frequency response more flat and sharp similar to ideal filter frequency response.  Sigma delta modulator CIC filter Second half band filter First half band filter Droop correction6.144 MHz384 KHz192 KHz96 KHz48 KHzInput Signal21 R160 R 22 R 23 RDroop correction filter is allocated to compensate pass band attenuation which is created by CIC filter. The frequency response of overall system will be shown in section 4.   2.1 CIC filters structure  The CIC filter consist of N stages of integrator and comb filter which are connected by a down sampler stage as shown in figure 1 in z domain. The CIC filter has the following transfer function:  101)()1()1()().()(RMkNkNNRMNCNI zzzzHzHzH       (1)  where N is the number of stage, M is the differential delay and R is the decimation factor.  In this paper, N, M and R have been chosen to be 5, 1 and 16 respectively to avoid overflow in each stages.  R111 zRMz1SF RFSdecimator CombIntegratorInput sample rateOutput sample rate  Fig. 2 One-stage of CIC filter block diagram  N, M and R are parameters to determine the register length requirements necessary to assure no data loss. Equation (1) can be express as follow:   From the equation, the maximum register growth/width, maxG can be expressed as:                                    NRMG max                          (3)  In other word, maxG  is the maximum register growth and a function of the maximum output magnitude due to the worst possible input conditions [3].  If the input data word length isinB , most significant bit (MSB) at the filter output, maxB is given by:                   ]1log[ 2max  inBRNB                 (4)  In order to reduce the data loss, normally the first stage of the CIC filter has maximum number of bit compared to the other stages. Since the integrator stage works at the highest oversampling rate with a large internal word length, decimation ratio and filter order increase which result in more power consumption and speed limitation.   2.2 Truncation for low power & high speed purpose  Truncation means estimating and removing Least Significant Bit (LSB) to reduce the area requirements on chip and power consumption and also increase speed of calculation. Although this estimation and removing introduces additional error, the error can be made small enough to be acceptable for DSP applications. Figure 2 illustrates five stages of the CIC filter when maxB  is 25 bit so truncation is applied to reduce register width. Matlab software helps to find word length in integrator and comb section.   1Z+++-Integrator 125 bit1Z++Integrator 222 bitR1Z++Integrator 320 bit1Z++Integrator 418 bit1Z++Integrator 516 bit161ZComb 116 bit+-1ZComb 216 bit+-1ZComb 316 bit+-1ZComb 416 bit+-1ZComb 516 bita_ins_out Fig. 3 Five-stages of truncated CIC filter include                                  integrator and comb cell  3 Speed Improvement   There are two ways to speed up the CIC filter which describes as below.  3.1 Pipeline structure  One way to have high speed CIC filter is by implementing the pipeline filter structure. Figure 4 shows pipeline CIC filter structure when truncation is also applied. In the pipelined structure, no additional pipeline registers are used. So that hardware requirement is the same as in the non-pipeline [6]. CIC decimation filter clock rate is determined by the first integrator stage that causes more propagation delay than any other stage due to maximum number of bit. So it is possible to use a higher clock rate for a CIC decimation filter if a pipeline structure is used in the integrator stages, as compared to non-pipelined integrator stages. Clock rate in integrator  NNRMkNRMkkNRMkkNRMkkNRMkkRMzzzzkhzH10101010)1(01)()(   (2) section is R times higher than in the comb section, so pipeline structure can not applied for comb section.   1ZR1Z1Z1Z1Z1Z1Z1Z1Z1Z+++-+++++++++-+- +-+-25 bit 22 bit 20 bit 18 bit 16 bit16inComb 116 bitComb 216 bitComb 316 bitComb 416 bitComb 516 bitoutIntegrator 1 Integrator 2 Integrator 3 Integrator 4 Integrator 5 Fig. 4 Five-stage of truncated pipeline CIC filter                        include integrator and comb cell   3.2 Modified Carry look-ahead Adder (MCLA)  The other technique to increase speed is using Modified Carry Look-ahead Adder. The Carry Look-ahead adder (CLA) is the fastest adder which can be used for speeding up purpose but the disadvantage of the CLA adder is that the carry logic is getting quite complicated for more than 4 bits so Modified Carry Look-ahead Adder (MCLA) is introduced to replace as adder. This improve in speed is due to the carry calculation in MCLA. In the ripple carry adder, most significant bit addition has to wait for the carry to ripple through from the least significant bit addition. Therefore the carry of MCLA adder has become a focus of study in speeding up the adder circuits [5]. The 8 bit MCLA structure is shown in Figure 6. Its block diagram consists of 2, 4-bit module which is connected and each previous 4 bit calculates carry out for the next carry. The CIC filter in this paper has five MCLA in integrator parts. The maximum number of bit is 25 and it is decreased in next stages. So it truncated respectively to 25, 22, 20, 18 and 16 bit in each adder, left to right Notice that each 4-bit adder provides a group Propagate and Generate Signal, which is used by the MCLA Logic block. The group Propagate PG and Generate GG of a 4-bit adder will have the following expressions:                           0123 ... ppppPG                              (5) 0123123233 ...... gpppgppgpgGG          (6)  The most important equations to obtain carry of each stage have been defined as below:                       ).( 0001 cpgc                                 (7)              )..().( 0010112 cppgpgc                    (8)  )..()..().( 0.0120121223 cpppgppgpgc   (9) )...()..().( 01231232334 gpppgppgpgc )....( 00123 cpppp  Calculation of MCLA is based on above equations. 8-Bit MCLA Adder could be constructed continuing along in the same logic pattern, with the MSB carry-out resulting from OR & AND gates. The Verilog code has been written to implement summation. The MCLA Verilog code was downloaded to the Xilinx FPGA chip.  It was found minimum clock period on FPGA board is 4.389ns (Maximum Frequency is 220 MHz).  a0b0p0g0a1b1p1g1a2b2p2c1c2a3b3p3g3CLL-1c3a5b5p5g5a6b6p6g6c6a7b7p7g7c7a4b4p4g4c4c5CLL-2c8c4s0s1s2g2s3PFAPFAPFAs5s6s7 s4PFA PFA PFAPFA Fig. 5 The 8 bit MCLA structure  4 Design Results  Figure 6 illustrate the frequency response of the CIC filter when the sampling frequency is 6.144 MHz and the pass band frequency is 348 KHz.  0 1 2 3 4 5 6 7x 105-160-140-120-100-80-60-40-200SINC FilterFrequency(Hz)Amplitude(dB)    Fig. 6 Comb filter frequency response for R=16,                                           M=1 and N=5 (10) After the sigma delta modulator, the sampling rate must be reduced to 47 KHz which is the Nyquist sampling rate. This is carried out in 4-stages. The first stage involves the reduction of the sampling frequency by the decimation factor of 16. This is done by the CIC filter.  The remaining 3 stages involve the reduction of the sampling frequency by the decimation factor of 2 only which are carried out by the first half band, droop correction and the second half band respectively. The Simulation results for all 4 stages are given in figure 7.        0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2x 105-160-140-120-100-80-60-40-200First Half-band FilterFrequency (Hz)Amplitude(dB)0 1 2 3 4 5 6 7 8 9 10x 104-160-140-120-100-80-60-40-200Droop Correction FilterFrequency (Hz)Amplitude(dB) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5x 104-160-140-120-100-80-60-40-200Second Half-band FilterFrequency (Hz)Amplitude(dB) 0 5 10 15 20 25 30 35 40 45 50-160-140-120-100-80-60-40-200Overal SystemFrequency (kHz)Amplitude(dB)  Fig. 7  frequency response of (a) first half band filter (b) droop correction (c) second half band filter (d) overall decimation process , Over sampling ratio=128   Figure 8 shows the measured baseband output spectra before (Figure 8(a)) and after (Figure 8(b)) the decimation functions.  The CIC filter Verilog code was written and simulated by Matlab software. It is found Signal to Noise ratio (SNR) is 141.56 dB in sigma delta modulator output and SNR is increased to 145.35 dB in the decimation stages. To improve the signal to noise ratio, word length of recursive CIC filter should be increased but the speed of filter calculation is also decreased.    (a) (a) (b) (c) (d)  (b)  Fig. 8 Signal spectra (a) Output sigma delta modulator                        SNR (b) Output CIC filter SNR  5 Conclusions  Recursive CIC filters have been designed and investigated. Enhanced high Speed CIC filters was obtained by the pipeline structure and by using the modified carry look-ahead adder (MCLA). The evaluation indicates that the pipelined CIC filter with MCLA adder is attractive due to high speed when both the decimation ratio and filter order are not high as stated in the Hogenauer Comb filter.  Since the first stage of CIC filter require maximum word length and also because of the recursive loop in its structure, thus power is limited by the calculation in integrator stage, so the truncation will reduced the power consumption to obtain high speed operation.   References [1] R.E.Crochiere and L.R. Rabiner, Multirate Digital Signal Processing, Engelwood Cliffs, Prentice Hall, New Jersey, 1983. [2] P.P. Vaidyanathan, Multirate Systems and Filter Banks, Engelwood Cliffs, Prentice Hall, New Jersey, 1993. [3] E.B. Hogenauer, An Economical Class of digital filters for Decimation and interpolation, IEEE Transactions on Acoustics, Speech, and Signal Prosessing, Vol. ASSP-29,pp.155-162, April 1981. [4] Sangil Park, Principles of Sigma-delta Modulation for Analog-to-Digital Converters, Motorola Inc, APR8/D Rev.1, 1990 [5] Michael D. Ciletti, Advanced Digital design with the Verilog HDL, Prentice Hall, Department of Electrical and Computer Engineering University of Colorado at Colorado Springs, 2003  [6] Y. Djadi and T. A. Kwasniewski, C. Chan and V. Szwarc, “A high throughput Programmable Decimation and Interpolation Filter”, Proceeding of International Conference on Signal Processing Applications and Technology, pp.1743-1748, 1994 [7] Brian P. Brandt and Bruce A. Wooley, A Low-Power, Area-Efficient Digital Filter for Decimation and Interpolation, IEEE Journal of Solid-State Circuits, Vol. 29, No.6, June 1994 

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VLSI Implementation of Cascaded Integrator Comb Filters for DSP Applications

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