25 research outputs found

    A Method for Sharing Traffic Jam Information using Inter-Vehicle Communication

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    V2VCOM2006 : Vehicle-to-Vehicle Communications , Jul 17-21, 2006 , San Jose, CA, USAIn this paper, we propose a method for cars to autonomously and cooperatively collect traffic jam statistics to estimate arrival time to destination for each car using inter-vehicle communication. In the method, the target geographical region is divided into areas, and each car measures time to pass through each area. Traffic information is collected by exchanging information between cars using inter-vehicle communication. In order to improve accuracy of estimation, we introduce several mechanisms to avoid same data to be repeatedly counted. Since wireless bandwidth usable for exchanging statistics information is limited, the proposed method includes a mechanism to categorize data, and send important data prior to other data. In order to evaluate effectiveness of the proposed method, we implemented the method on a traffic simulator NETSTREAM developed by Toyota Central R&D Labs, conducted some experiments and confirmed that the method achieves practical performance in sharing traffic jam information using inter-vehicle communication

    A Technique for Information Sharing using Inter-Vehicle Communication with Message Ferrying

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    MDM'06 : 7th International Conference on Mobile Data Management , May 9-12, 2006 , Nara, JapanIn this paper, we propose a method to realize traffic information sharing among cars using inter-vehicle communication. When traffic information on a target area is retained by ordinary cars near the area, the information may be lost when the density of cars becomes low. In our method, we use the message ferrying technique together with the neighboring broadcast to mitigate this problem. We use buses which travel through regular routes as ferries. We let buses maintain the traffic information statistics in each area received from its neighboring cars. We implemented the proposed system, and conducted performance evaluation using traffic simulator NETSTREAM. As a result, we have confirmed that the proposed method can achieve better performance than using only neighboring broadcast

    A Proposal Of Hierarchical Chordal

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    This paper presents a hierarchical chordal ring network topology (HCRN) as a regular logical topology for multihop WDM networks. In order to minimize the traffic increase and the transmission delay through the network due to packet relays or hops on intermediate nodes in the multihop network, the network topology is hierarchically constructed in HCRN, so that more lightpaths are assigned to connections between nearby nodes than those for distant nodes, while the maximum hop between any pair of nodes is restrained. This hierarchical topology is also beneficial to reduce the number of required wavelengths through increasing their reuses by multiple lightpaths, which is important for cost-conscious metropolitan area networks. Through comparisons on the network diameter and the number of required wavelengths with the original chordal ring network topology, we show the effectiveness of our proposed HCRN

    Studies of Human Tγ Cells: Division of a Tγ Subset in Normal and Leukemic Cells by Using Anti-Tγ-CLL Heteroantiserum

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    Design and Implementation of Priority Queuing Mechanism on FPGA using Concurrent Periodic EFSMs and Parametric Model Checking

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    In this paper, we propose a design and implementation method for priority queuing mechanisms on FPGAs. First, we describe behavior of WFQ (weighted fair queuing) with several parameters in a model called concurrent periodic EFSMs. Then, we derive a parameter condition for the concurrent EFSMs to execute their transitions without deadlocks in the specified time period repeatedly under the specified temporal constraints, using parametric model checking technique. From the derived parameter condition, we can decide adequate parameter values satisfying the condition, considering total costs of components. Based on the proposed method, high-reliable and high-performance WFQ circuits for gigabit networks can be synthesized on FPGAs
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