Partitionnement automatique optimisant les ressources FPGA pour l'aide à la conception de SoC reconfigurable

- Nous proposons un outil permettant d'aider les concepteurs lors de la mise en place d'algorithmes utilisant la reconfiguration dynamique. Il permet de trouver la meilleure adéquation entre une application et son implantation sur un SOC reconfigurable. Reposant sur un partitionnement temporel original, il vise différents objectifs : minimisation des ressources logiques et minimisation de la bande passante mémoire

Robust hyperchaotic synchronization via analog transmission line

In this paper, a novel experimental chaotic synchronization technique via analog transmission is discussed. We demonstrate through Field-Programmable Gate Array (FPGA) implementation design the robust synchronization of two embedded hyperchaotic Lorenz generators interconnected with an analog transmission line. The basic idea of this work consists in combining a numerical generation of chaos and transmitting it with an analog signal. The numerical chaos allows to overcome the callback parameter mismatch problem and the analog transmission offers robust data security. As application, this technique can be applied to all families of chaotic systems including time-delayed chaotic systems

Temporal partitioning methodology optimizing FPGA resources for dynamically reconfigurable embedded real-time system

International audienc

CuNoC: A dynamic scalable communication structure for dynamically reconfigurable FPGAs

International audienc

Power energy output prediction of small wind urban for decision making

International audienc

Smart greenhouse fuzzy logic based control system enhanced with wireless data monitoring

Greenhouse climate control is complicated procedure since the number of variables involved on it and which are dependent on each other. This paper presents a contribution to integrate greenhouse inside climate keys parameters, leading to promote a comfortable micro-climate for the plants growth while saving energy and water resources. A smart fuzzy logic based control system was introduced and improved through specific measure to the temperature and humidity correlation. As well, the system control was enhanced with wireless data monitoring platform for data routing and logging, which provides real time data access. The proposed control system was experimentally validated. The efficiency of the system was evaluated showing important energy and water savings

Linear array processors with multiple access modes memory for real-time image processing

International audienc

Implementation of Universal Digital Architecture using 3D-NoC for Mobile Terminal

International Conference on Control, Decision and Information Technologies (CoDIT), Ecole Natl Ingenieurs Metz, Metz, FRANCE, NOV 03-05, 2014International audienceThe need to integrate multiple wireless communication protocols into a single low-cost flexible hardware platform is prompted by the increasing number of emerging communication protocols and applications in modern embedded systems. So the current challenge is to design of new digital architectures, in addition to its ability to take over of many functions. In this paper we have identified similarities between the despreader units in Rake receiver and the processor element in FFT-SDF (Fast Fourier Transform-Single path Delay Feedback) to propose a generic architecture shared between the two algorithms widely used. This Smart architecture is interconnected with similar modules by a 3D Network-on-Chip for implementation of Rake receiver (used in WCDMA system) and FFT receiver (in OFDM system). We present in this paper a 3D-NoC with half layer-layer connection, this architecture uses a modified XYZ routing algorithm. The proposed architectures are coded using VHDL onto a Virtex 5 Field-Programmable Gate Array (FPGA) device and results are compared with similar works. The implementation demonstrates that the proposed architectures can deliver a high reduction of the FPGA logic requirements with high maximum frequency

Custom instruction generation using temporal partitioning techniques for a reconfigurable functional unit

Abstract. Extracting appropriate custom instructions is an important phase for implementing an application on an extensible processor with a reconfigurable functional unit (RFU). Custom instructions (CIs) are usually extracted from critical portions of applications. It may not be possible to meet all of the RFU constraints when CIs are generated. This paper addresses the generation of mappable CIs on an RFU. In this paper, our proposed RFU architecture for an adaptive dynamic extensible processor is described. Then, an integrated framework for temporal partitioning and mapping is presented to partition and map the CIs on RFU. In this framework, two mapping aware temporal partitioning algorithms are used to generate CIs. Temporal partitioning iterates and modifies partitions incrementally to generate CIs. Using this framework brings about more speedup for the extensible processor. 1

Reliable Router for accurate Online Error Detection in Dynamic Network on Chip

25th International Conference on Microelectronics (ICM), Beirut, LEBANON, DEC 15-18, 2013International audienceThis paper proposes a new reliable router allowing accurate online error detections in dynamic Network on Chip (NoC). The proposed router has the capability to detect and localize accurately inner or outer data packet errors of the router while distinguish between temporary and permanently errors. The error detection mechanisms of the proposed switches and advantages with regards to the other main already proposed router approaches are detailed while proving the feasibility and efficiency through several simulations online detection cases. Performance evaluation and FPGA implementation results are also given