3D integration technologies

3D integration is a key solution to the predicted performance problems of future ICs as well as it offers extreme miniaturization and cost-effective fabrication of More than Moore products (e.g. e-CUBES (R)). Through Silicon Via (TSV) technologies enable high interconnect performance at relatively high fabrication cost compared to 3D packaging. A post backend-of-line TSV process is introduced as optimized technology for More than Moore products: The ICV-SLID process enables 3D integration of completely fabricated devices. Reliability issues, as thermo-mechanical stress caused by TSV formation and bonding are considered. The technology choice for the e-CUBES automotive application demonstrator is described

3D interconnect technologies for advanced MEMS/NEMS applications

3D integration and wafer level packaging (WLP) with through-silicon vias offer benefits like reduced footprint and improved performance. CMOS imaging sensors is one of the first successful introductions of a product with TSVs on the market, and 3D integrated memory stacks are expected to follow soon. Also sensor and actuator systems based on micro- and nano-electromechanical systems (MEMS/NEMS) will greatly benefit from WLP and 3D integration of the transducers and their readout and controller ICs. Ultimately, heterogeneous integration of different device technologies will allow the fabrication of MEMS/IC and NEMS/IC products with new and improved functionalities. For this to become a reality, cost-effective and reliable 3D integration technologies need to be developed. This paper gives an overview and reports on the current status of 3D interconnect technologies that will enable 3D integration for advanced MEMS/NEMS applications

Characterization of hermetic wafer-level Cu-Sn SLID bonding

A flux-less copper-tin (Cu-Sn) solid-liquid inter-diffusion (SLID) bonding process, providing a cost-effective hermetic vacuum sealing at wafer-level, has been investigated. Observations have been made indicating that the storage time of Cu-Sn plated wafers before bonding is critical with regard to voiding. Growth of the intermediately formed intermetallic compound (IMC), Cu 6Sn5, was investigated as a possible cause. Room temperature aging of Cu-Sn plated wafers prior to bonding was performed as well as annealing of un-bonded Cu-Sn plated wafers. The presence of large Cu 6Sn5 and Cu3Sn crystallites which nearly depleted the Sn was observed by optical microscopy after annealing. If large Cu6Sn5 grains from opposite contact planes meet at the bond interface, voids are predicted to be formed during the subsequent stages of liquid inter-diffusion and solidification. Implications on the Cu-Sn bonding strategy based on the results are presented

Void formation and bond strength investigated for wafer-level Cu-Sn solid-liquid interdiffusion (SLID) bonding

A hermetic wafer-level Cu-Sn solid-liquid interdiffusion (SLID) bonding was investigated to explore the sensitivity of selected process parameters with regard to voiding and possible reduction of strength. Little or no variation was observed in the void density as a result of modifying the plated Sn-thickness, the storage time between plating and bonding, the bonding tool pressure, or the thermal budget during bonding. All shear tested samples showed excellent shear strength, with an average of 110-164 MPa. Some statistically significant differences in shear strength were found between the varied process parameters. However, the differences were too small to be critical for the application. Analysis of fracture surfaces showed that shear strengths in the lower range corresponded to fracture between the adhesion layer (TiW) and the silicon cap, while shear strengths in the higher range corresponded to fracture in the Cu3Sn formed during the bonding. The results indicate that the bonding process is robust with regard to the studied process parameters

Residual stress in silicon caused by Cu-Sn wafer-level packaging

The level of stress in silicon as a result of applying Cu-Sn SLID wafer level bonding to hermetically encapsulate a highperformance infrared bolometer device was studied. Transistors are present in the read out integrated circuit (ROIC) of the device and some are located below the bond frame. Test vehicles were assembled using Cu-Sn SLID bonding and micro- Raman spectroscopy was applied on cross sectioned samples to measure stress in the silicon near the bond frame. The test vehicles contained cavities and the bulging of the structures was studied using white light interferometry. The test vehicles were thermally stressed to study possible effects of the treatments on the level of stress in the silicon. Finite element modeling was performed to support the understanding of the various observations. The measurements indicated levels of stress in the silicon that can affect transistors in regions up to 15 μm below the bond frame. The observed levels of stress corresponded well with the performed modeling. However, no noticeable effect was found for the ROIC used in this work. The specific technology used for the fabrication of the ROIC of a MEMS device is thus decisive. The level of stress did not appear to change as a result of the imposed thermal stress. The level of stress caused by the bond frame can be expected to stay constant throughout the lifetime of a device. Copyright © 2013 by ASME