Ultra-High-Speed Image Signal Accumulation Sensor

Averaging of accumulated data is a standard technique applied to processing data with low signal-to-noise ratios (SNR), such as image signals captured in ultra-high-speed imaging. The authors propose an architecture layout of an ultra-high-speed image sensor capable of on-chip signal accumulation. The very high frame rate is enabled by employing an image sensor structure with a multi-folded CCD in each pixel, which serves as an in situ image signal storage. The signal accumulation function is achieved by direct connection of the first and the last storage elements of the in situ storage CCD. It has been thought that the multi-folding is achievable only by driving electrodes with complicated and impractical layouts. Simple configurations of the driving electrodes to overcome the difficulty are presented for two-phase and four-phase transfer CCD systems. The in situ storage image sensor with the signal accumulation function is named Image Signal Accumulation Sensor (ISAS)

Toward the Ultimate-High-Speed Image Sensor: From 10 ns to 50 ps

The paper summarizes the evolution of the Backside-Illuminated Multi-Collection-Gate (BSI MCG) image sensors from the proposed fundamental structure to the development of a practical ultimate-high-speed silicon image sensor. A test chip of the BSI MCG image sensor achieves the temporal resolution of 10 ns. The authors have derived the expression of the temporal resolution limit of photoelectron conversion layers. For silicon image sensors, the limit is 11.1 ps. By considering the theoretical derivation, a high-speed image sensor designed can achieve the frame rate close to the theoretical limit. However, some of the conditions conflict with performance indices other than the frame rate, such as sensitivity and crosstalk. After adjusting these trade-offs, a simple pixel model of the image sensor is designed and evaluated by simulations. The results reveal that the sensor can achieve a temporal resolution of 50 ps with the existing technology

The Theoretical Highest Frame Rate of Silicon Image Sensors

The frame rate of the digital high-speed video camera was 2000 frames per second (fps) in 1989, and has been exponentially increasing. A simulation study showed that a silicon image sensor made with a 130 nm process technology can achieve about 1010 fps. The frame rate seems to approach the upper bound. Rayleigh proposed an expression on the theoretical spatial resolution limit when the resolution of lenses approached the limit. In this paper, the temporal resolution limit of silicon image sensors was theoretically analyzed. It is revealed that the limit is mainly governed by mixing of charges with different travel times caused by the distribution of penetration depth of light. The derived expression of the limit is extremely simple, yet accurate. For example, the limit for green light of 550 nm incident to silicon image sensors at 300 K is 11.1 picoseconds. Therefore, the theoretical highest frame rate is 90.1 Gfps (about 1011 fps

Monolithic CMOS sensors for sub-nanosecond timing

In the ATTRACT project FASTPIX we investigate monolithic pixel sensors with small collection electrodes in CMOS technologies for fast signal collection and precise timing in the sub-nanosecond range. Deep submicron CMOS technologies allow tiny, sub-femtofarad collection electrodes, and large signal-to-noise ratios, essential for very precise timing. However, complex in-pixel circuits require some area, and one ofthe key limitations for precise timing is the longer drift time of signal charge generated near the pixel borders.Laying out the collection electrodes on a hexagonal grid and reducing the pixel pitch minimize the maximumdistance from the pixel border to the collection electrode. The electric field optimized with TCAD simulationspulls the signal charge away from the pixel border towards the collection electrode as fast as possible. Thisalso reduces charge sharing and maximizes the seed pixel signal hence reducing time-walk effects. Here thehexagonal geometry also contributes by limiting charge sharing at the pixel corners to only three pixels insteadof four. We reach pixel pitches down to about 8.7 μmbetween collection electrodes in this 180 nm technologyby placing only a minimum amount of circuitry in the pixel and the rest at the matrix periphery. Consumingseveral tens of micro-ampere per pixel from a 1.8 V supply offers a time jitter of only a few tens of picoseconds.This allows detailed characterization of the sensor timing performance in a prototype chip with several minimatrices of 64 pixels each with amplifier, comparator and digital readout and 4 additional pixels with analogbuffers. The aim is to prove sensor concepts before moving to a much finer line width technology and fullyintegrate the readout within the pixel at lower power consumption

A Pixel Design of a Branching Ultra-Highspeed Image Sensor

A burst image sensor named Hanabi, meaning fireworks in Japanese, includes a branching CCD and multiple CMOS readout circuits. The sensor is backside-illuminated with a light/charge guide pipe to minimize the temporal resolution by suppressing the horizontal motion of signal carriers. On the front side, the pixel has a guide gate at the center, branching to six first-branching gates, each bifurcating to second-branching gates, and finally connected to 12 (=6×2) floating diffusions. The signals are either read out after an image capture operation to replay 12 to 48 consecutive images, or continuously transferred to a memory chip stacked on the front side of the sensor chip and converted to digital signals. A CCD burst image sensor enables a noiseless signal transfer from a photodiode to the in-situ storage even at very high frame rates. However, the pixel count conflicts with the frame count due to the large pixel size for the relatively large in-pixel CCD memory elements. A CMOS burst image sensor can use small trench-type capacitors for memory elements, instead of CCD channels. However, the transfer noise from a floating diffusion to the memory element increases in proportion to the square root of the frame rate. The Hanabi chip overcomes the compromise between these pros and cons

Toward 100 Mega-Frames per Second: Design of an Ultimate Ultra-High-Speed Image Sensor

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