The Preparation of Non-aqueous Supercapacitors with Lithium Transition-Metal Oxide/Activated Carbon Composite Positive Electrodes

In order to increase the specific capacitance and energy density of supercapacitors, non-aqueous supercapacitors were prepared using lithium transition-metal oxides and activated carbons as active materials The electrochemical properties were analyzed in terms of the content of lithium transition-metal oxides The results of cyclic voltammetry and AC-impedance analyses showed that the pseudocapacitance may stem from the synergistic contributions of capacitive and faradic effects, the former is due to the electric double layer which is prepared in the interface of activated carbon and organic electrolyte, and the latter is due to the intercalation of lithium (Li+)ions The specific capacitance and energy density of a supercapacitor improved as the lithium transition-metal oxides content increased, showing 60% increase compared to those of supercapacitor using a pure activated carbon positive electrodopen4

A Router for Symmetrical FPGAs based on Exact Routing Density Evaluation

Abstract This paper presents a new performance and routability driven routing algorithm for symmetrical array based field-programmable gate arrays (FPGAs). A key contribution of our work is to overcome one essential limitation of the previous routing algorithms: inaccurate estimations of routing density which were too general for symmetrical FPGAs. To this end, we derive an exact routing density calculation that is based on a precise analysis of the structure (switch block) of symmetrical FPGAs, and utilize it consistently in global and detailed routings. With an introduction of the proposed accurate routing metrics, we design a new routing algorithm called a cost-effective net-decomposition based routing which is fast, and yet produces remarkable routing results in terms of both routability and path/net delays. We performed an extensive experiment to show the effectiveness of our algorithm based on the proposed cost metrics

Experimental Study on Flow Control Characteristics of Synthetic Jets over a Blended Wing Body Configuration

Nov. 20-22, 2013, Sunport Hall Takamatsu, Takamatsu, JAPANThis paper presents experimental investigations on the characteristics of synthetic jets over blended wing body configuration. Flow control experiments were performed by using piezoelectrically driven synthetic jet under various flow conditions. In the first step, baseline characteristics of blended wing body configuration were analyzed when synthetic jet was off. Pressure distribution and separated-flow region on the wing surface were examined by changing the angle of attack. Flow control experiments were carried out by synthetic jet to demonstrate the flow control performance in the post-stall regime. Comparative studies were also conducted for a stalled condition. Aerodynamic coefficient was examined by changing synthetic jet operating condition, such as jet oscillation frequency and jet module locations. Based on various comparisons, it was observed that synthetic jet operating conditions have significantly influence on the development of leading-edge vorticies, that is to say, flow control performance of synthetic jet.This research was supported by Defense Acquisition Program Administration and Agency for Defense Development (UC100031JD).OAIID:oai:osos.snu.ac.kr:snu2013-01/104/0000004648/20SEQ:20PERF_CD:SNU2013-01EVAL_ITEM_CD:104USER_ID:0000004648ADJUST_YN:NEMP_ID:A001138DEPT_CD:446CITE_RATE:0FILENAME:api280_bhl_130913.pdfDEPT_NM:기계항공공학부EMAIL:[email protected]:

Scheduling and allocation problems in high-level synthesis

Various aspects of the two major tasks in high-level synthesis, scheduling and allocation, are studied in this thesis. Specifically, we study (1) the problem of scheduling dataflow graphs with conditional branches; (2) the problem of utilizing multi-port memories in data path synthesis; (3) the problem of integrating the scheduling and allocation steps; and (4) the problem of data path synthesis for testability.U of I OnlyETDs are only available to UIUC Users without author permissio

Pin Accessibility-driven Placement Optimization with Accurate and Comprehensive Prediction Model

The significantly increased density of pins of standard cells and the reduced number of routing tracks at sub-10nm nodes have made the pin access problem in detailed routing very difficult. To alleviate this pin accessibility problem in detailed routing, recent works have proposed to make a small perturbation of cell shifting, cell flipping, and adjacent cells swapping in the detailed placement stage. Here, an essential element for the success of pin accessibility aware detailed placement is the installed cost function, which should be sufficiently accurate in predicting the degree of routing difficulty in accessing pins. In this work, we propose a new model of cost function that is comprehensively devised to overcome the limitations of the prior ones. Precisely, unlike the conventional cost functions, our proposed cost function model is based on the empirical routing data in order to fully reflect the potential outcomes of detailed routing. Through experiments with benchmark circuits, it is shown that using our proposed cost function in detailed placement is able to reduce the routing errors by 44% on average while using the existing cost functions reduce the routing errors on average by at most 15%.N

Practical Approach to Cell Replacement for Resolving Pin Inaccessibility

We propose a practical approach to the cell replacement problem for resolving the pin inaccessibility in the ECO (engineering-change-order) routing stage. The prior cell replacement method performs in two steps: (i) it prepares a subsidiary (i.e., alternative) cell library that includes for each cell type a set of diverse cell layouts. Then, (ii) it iteratively tries to replace the cells of routing failures with some cells in the subsidiary library during ECO routing in order to fix the routing failures. In this work, we downsize the subsidiary library produced in step (i) to speed up the sequential and time-consuming process of step (ii). Precisely, we propose a function based on the well-known formulation of Levenshtein distance to measure the degree of the pin topology difference between the layout of a cell type in the target library and a layout of the same type in the subsidiary library. Then, we update the subsidiary library to include, for each cell type, exactly one layout that has the biggest pin topology difference. Through experiments with benchmark circuits, it is shown that using the subsidiary library produced by our topology difference formulation enables to reduce the number of trials of cell replacements significantly over the conventional method while fixing almost the same amount of routing violations.N

Improving Speed of MUX-FSM-based Stochastic Computing for On-device Neural Networks

© 2022. The Korean Institute of Information Scientists and EngineersWe propose an acceleration technique for processing multiplication operations using stochastic computing (SC) in ondevice neural networks. Recently, multiplexor driven finite state machine (MUX-FSM)-based SCs, which employ a MUX controlled by an FSM to generate a (repeated but short) bit sequence of a binary number to count up for a multiplication operation, considerably reduce the processing time of MAC operations over the traditional stochastic number generator (SNG) based SC. Nevertheless, the existing MUX-FSM-based SCs still do not meet the multiplication processing time required for the wide adoption of on-device neural networks in practice even though it offers a very economical hardware implementation. In this respect, this work proposes a solution that speeds up the conventional MUX-FSMbased SCs. Precisely, we analyze the bit counting pattern produced by MUX-FSM and replace the counting redundancy by shift operation, resulting in a shortening of the length of the required bit sequence significantly, together with analytically formulating the number of computation cycles. Through experiments, we have shown that the enhanced SC technique can reduce the processing time by 44.1% on average over the conventional MUX-FSM-based SCs.N

Utilizing Middle-of-Line Resource in Filler Cells for Fixing Routing Failures

As the process technology progresses, it becomes much hard to make a complete routing for all nets in chip implementation. Consequently, lots of effort is devoted to the ECO (engineering-change-order) routing to fix the routing failures. In this paper, we propose to use the LISD (local interconnect to source/drain) metal resource in the middle-of-line (MOL) layer of filler cells. So far, no previous work has addressed the problem of using LISD resource in filler cells for routing. For each of unroutable nets, we perform the following three steps: (1) we collects all the filler cells in the bounding box of the target net terminals, (2) we replace the routing segments that pass over the filler cells extracted in step 1 with LISD metals to make more metals on top of LISD available to use for routing, and (3) we then apply a conventional ECO router to the target net. Through experiments with benchmark circuits, it is shown that our proposed ECO router that utilizes the LISD metal resource in MOL layer is able to produce chip implementations with on average 21.43% less number of routing failures over the implementations without using LISD resource.N

Flip-flop State Driven Clock Gating: Concept, Design, and Methodology

Flip-flop's input data toggling based clock gating is one of the most widely used clock gating methods, in which one critical and inherent limitation is the sharp increase of gating logic as more flip-flops are gating. In this work, we propose a new clock gating method to overcome this limitation. Precisely, (1) we analyze the resources of gating logic in the input data toggling based clock gating, from which an ineffectiveness in resource utilization is observed and we propose a new clock gating technique called flip-flop state driven clock gating which completely eliminates the essential and expensive component of XOR gates for detecting input toggling of flip-flops; (2) we provide the supporting logic circuitry of our proposed XOR-free clock gating, confirming its safe applicability through a comprehensive timing analysis; (3) we propose, based on the flip-flops' state profile, a clock gating methodology that seamlessly combines our flip-flop state based clock gating with the toggling based clock gating. Through experiments with benchmark circuits, it is confirmed that our clock gating method is very effective in reducing power, which otherwise the toggling based clock gating shall miss the power saving opportunity, while meeting all timing constraints.N