Force-Directed Partitioning Technique for 3D IC

3D IC design is one of the challenging problems of today. 3D partitioning solutions can significantly impact manufacturability and performance of a circuit. In this work, a 3D partitioning technique is developed that reduces the number of TSVs by using force directed placement technique. A circuit is partitioned into several layers and a force directed placement problem is solved to find the optimal locations of the partitions. This partitioning solution is improved by using a proposed force-based simulated annealing technique. The proposed technique is tested on ISPD04 circuits, and shows up to 20% reduction in the number of TSVs

A Machine Learning Predictor and Corrector Framework to Identify and Resolve VLSI Routing Short Violations

The growth of Very Large Scale Integration (VLSI) technology provokes new challenges in design automation of Integrated Circuits (ICs). Routability is one of the most challenging aspects in Electronic Design Automation (EDA) that is faced in two consecutive phases of physical design: placement and routing. During placement, the exact locations of circuit components are determined. During routing the paths for all of the wires are specified. Routing is performed in two stages: global routing and detailed routing. Many of the violations that occur during the detailed routing stage stem from ignoring the routing rules during placement. Therefore, detecting and preventing routing violations in the placement stage has become critical in reducing the design time and the possibility of failure. In this thesis, Eh?Predictor, a deep learning framework to predict detailed routing short violations during placement is proposed. In the development of this predictor, relevant features, contributing to routing violations, were identified, extracted, and analyzed. A neural network model that can handle imbalanced data was customized to detect these violations using the defined features. The proposed predictor can be integrated into a placement tool and be used as a guide during the placement process to reduce the number of shorts happening in the detailed routing stage. One of the advantages of this technique is that by using the proposed deep learning-based predictor, global routing is no longer required as frequently. Hence the total runtime for place and route can be significantly reduced. In addition to Eh?Predictor, a detailed routing-aware detailed placement algorithm is developed to improve detailed routability in a relatively short runtime. The proposed technique is referred to as Detailed Routing-aware Detailed Placer (DrDp). DrDp is a heuristic that aims to reduce the local congestion and mitigate routing failure by aligning the connected cells where possible at the final stage of detailed placement process. Experimental results show that Eh?Predictor is able to predict on average 90% of the short violations of previously unseen data with only 5% false alarm rate and considerably reduce computational time, and DrDp can effectively improve the detailed routing quality in a short runtime with no significant change in detailed placement score or total wirelength