Parametric Timing Analisys and Its Appication to Dynamic Voltage Scaling

Embedded systems with real-time constraints depend on a priori knowledge of worst-case execution times (WCETs) to determine if tasks meet deadlines. Static timing analysis derives bounds on WCETs but requires statically known loop bounds. This work removes the constraint on known loop bounds through parametric analysis expressing WCETs as functions. Tighter WCETs are dynamically discovered to exploit slack by dynamic voltage scaling (DVS) saving 60% to 82% energy over DVS-oblivious techniques and showing savings close to more costly dynamic-priority DVS algorithms. Overall, parametric analysis expands the class of real-time applications to programs with loop-invariant dynamic loop bounds while retaining tight WCET bounds.This work was conducted at North Carolina State University and Florida State University; it was supported in part by NSF grants CCR-0208581, CCR-0310860, CCR-0312695, EIA-0072043, CCR-0208892, CCR-0312493 and CCR-0312531.Mohan, S.; Mueller, F.; Root, M.; Hawkins, W.; Healy, C.; Whalley, D.; Vivancos Rubio, E. (2011). Parametric Timing Analisys and Its Appication to Dynamic Voltage Scaling. ACM Transactions on Embedded Computing Systems. 10(2):1-34. doi:10.1145/1880050.1880061S13410