Market efficiency and information flow between the crude palm oil and crude oil futures markets

This study analyzes the efficiency of the crude palm oil (CPO) futures market by conducting a variance ratio test and comparing it to the West Texas Intermediate (WTI) futures market. We discover that the weak-form efficient market hypothesis holds for both the CPO and WTI futures markets despite the significant difference in their liquidity. Using a scaling exponent, we investigate speculative trading activities and find that trading CPO futures in expectation of significant returns does not strongly involve a high level of risk unlike WTI futures. Our findings regarding market efficiency of the two futures markets are supported by the significant integration of the two with similar level of information flow from each market to the other. To explore the role of speculation in their market integration, we introduce a natural experimental setting using the coronavirus disease 2019 (COVID-19) pandemic, which caused a sudden decrease in the demand for fuel. The bidirectional information flow between the two markets is intensified after the COVID-19 pandemic due to lower level of speculation. The findings suggest that (i) stakeholders in the CPO market need to pay attention to the crude oil markets to anticipate its price changes, (ii) investors can use WTI futures as a hedging tool against CPO futures as long as there is mutual information flow, and (iii) regulators should carefully implement new CPO futures market policy, as either asymmetric changes in speculation or unbalanced regulation with the WTI futures market can create market distortion and regulatory arbitrage

A flexible communication architecture to support multimedia services in high speed network

There have been research works on supporting QoS (Quality of Service) in a distributed multimedia systems. These researches can be categorized as following; system platform, real-time operating system, transport protocol, communication architecture. In distributed multimedia environment, QoS must be guaranteed in end systems, but much less progress has been made in addressing this problem. As the processing power of end systems increases, most of the bottleneck occurs in communication protocol, especially transport protocol. To meet an end-to-end QoS, overall QoS architectures must be integrated. In this paper, we propose a new QoS architecture and control mechanisms (group control, and flow control) to guarantee an end-to-end QoS for distributed multimedia services. We also verify proposed architecture by applying them to a multimedia conferencing system in LAN

A 0.8-to-2.3GHz Quadrature Error Corrector with Correctable Error Range of 101.6ps Using Minimum Total Delay Tracking and Asynchronous Calibration On-Off Scheme for DRAM Interface

As data transfer rates increase, clock frequencies used for high-speed data paths also increase. Thus, multiphase clocks are typically utilized in DRAMs to relax timing margins because of the reduced timing budget. However, phase errors between multiphase clocks, due to device mismatch, degrade the valid data sampling window. To reduce phase error, several multiphase correction schemes have been proposed [1]-[4]. The active poly-phase filter-based open-loop scheme exhibits a small RMS jitter contribution, but the remaining phase error after the error correction is considerably varied and large in its operating frequency range [1]. A distributed delay-locked loop (DLL) [2] offers the smallest RMS jitter, but the residual phase error is non-negligible as well due to the mismatch of error detection circuits in each calibration loop. The phase error corrector with a relaxation oscillator-based phase detector is also susceptible to the mismatch [3]. The digital DLL-based scheme adopts a shared digital feedback loop to eliminate the effect of mismatch [4]. However, it shows a larger RMS jitter contribution than the distributed DLL due to quantization noise and the increased clock path delay. Since the delay of in-phase clock is always fixed at the mid-point, overall set of codes of digitally-controlled delay lines (DCDLs) may not be at their optimum in terms of jitter. Because jitter and total delay of clock paths are increased more than necessary, it leads to degradation of the data eye. In this paper, an improved quadrature error corrector (QEC), the calibration of which starts from the minimum delay code over all DCDLs, is proposed along with an asynchronous and seamless-calibration on-off scheme for the reduction of power consumption in the operating state after calibration.N