Timing speculation and adaptive reliable overclocking techniques for aggressive computer systems

Computers have changed our lives beyond our own imagination in the past several decades. The continued and progressive advancements in VLSI technology and numerous micro-architectural innovations have played a key role in the design of spectacular low-cost high performance computing systems that have become omnipresent in today\u27s technology driven world. Performance and dependability have become key concerns as these ubiquitous computing machines continue to drive our everyday life. Every application has unique demands, as they run in diverse operating environments. Dependable, aggressive and adaptive systems improve efficiency in terms of speed, reliability and energy consumption. Traditional computing systems run at a fixed clock frequency, which is determined by taking into account the worst-case timing paths, operating conditions, and process variations. Timing speculation based reliable overclocking advocates going beyond worst-case limits to achieve best performance while not avoiding, but detecting and correcting a modest number of timing errors. The success of this design methodology relies on the fact that timing critical paths are rarely exercised in a design, and typical execution happens much faster than the timing requirements dictated by worst-case design methodology. Better-than-worst-case design methodology is advocated by several recent research pursuits, which exploit dependability techniques to enhance computer system performance. In this dissertation, we address different aspects of timing speculation based adaptive reliable overclocking schemes, and evaluate their role in the design of low-cost, high performance, energy efficient and dependable systems. We visualize various control knobs in the design that can be favorably controlled to ensure different design targets. As part of this research, we extend the SPRIT3E, or Superscalar PeRformance Improvement Through Tolerating Timing Errors, framework, and characterize the extent of application dependent performance acceleration achievable in superscalar processors by scrutinizing the various parameters that impact the operation beyond worst-case limits. We study the limitations imposed by short-path constraints on our technique, and present ways to exploit them to maximize performance gains. We analyze the sensitivity of our technique\u27s adaptiveness by exploring the necessary hardware requirements for dynamic overclocking schemes. Experimental analysis based on SPEC2000 benchmarks running on a SimpleScalar Alpha processor simulator, augmented with error rate data obtained from hardware simulations of a superscalar processor, are presented. Even though reliable overclocking guarantees functional correctness, it leads to higher power consumption. As a consequence, reliable overclocking without considering on-chip temperatures will bring down the lifetime reliability of the chip. In this thesis, we analyze how reliable overclocking impacts the on-chip temperature of a microprocessor and evaluate the effects of overheating, due to such reliable dynamic frequency tuning mechanisms, on the lifetime reliability of these systems. We then evaluate the effect of performing thermal throttling, a technique that clamps the on-chip temperature below a predefined value, on system performance and reliability. Our study shows that a reliably overclocked system with dynamic thermal management achieves 25% performance improvement, while lasting for 14 years when being operated within 353K. Over the past five decades, technology scaling, as predicted by Moore\u27s law, has been the bedrock of semiconductor technology evolution. The continued downscaling of CMOS technology to deep sub-micron gate lengths has been the primary reason for its dominance in today\u27s omnipresent silicon microchips. Even as the transition to the next technology node is indispensable, the initial cost and time associated in doing so presents a non-level playing field for the competitors in the semiconductor business. As part of this thesis, we evaluate the capability of speculative reliable overclocking mechanisms to maximize performance at a given technology level. We evaluate its competitiveness when compared to technology scaling, in terms of performance, power consumption, energy and energy delay product. We present a comprehensive comparison for integer and floating point SPEC2000 benchmarks running on a simulated Alpha processor at three different technology nodes in normal and enhanced modes. Our results suggest that adopting reliable overclocking strategies will help skip a technology node altogether, or be competitive in the market, while porting to the next technology node. Reliability has become a serious concern as systems embrace nanometer technologies. In this dissertation, we propose a novel fault tolerant aggressive system that combines soft error protection and timing error tolerance. We replicate both the pipeline registers and the pipeline stage combinational logic. The replicated logic receives its inputs from the primary pipeline registers while writing its output to the replicated pipeline registers. The organization of redundancy in the proposed Conjoined Pipeline system supports overclocking, provides concurrent error detection and recovery capability for soft errors, intermittent faults and timing errors, and flags permanent silicon defects. The fast recovery process requires no checkpointing and takes three cycles. Back annotated post-layout gate-level timing simulations, using 45nm technology, of a conjoined two-stage arithmetic pipeline and a conjoined five-stage DLX pipeline processor, with forwarding logic, show that our approach, even under a severe fault injection campaign, achieves near 100% fault coverage and an average performance improvement of about 20%, when dynamically overclocked

24 GHz low-power switch-channel CMOS transceiver for wireless localization

Dieser Beitrag ist mit Zustimmung des Rechteinhabers aufgrund einer (DFG geförderten) Allianz- bzw. Nationallizenz frei zugänglich.This publication is with permission of the rights owner freely accessible due to an Alliance licence and a national licence (funded by the DFG, German Research Foundation) respectively.A 24 GHz low-power transceiver is designed, fabricated, and characterized using 130 nm complementary metal-oxide semiconductor (CMOS) process. The designed transceiver is targeted for frequency-modulated-continuous-wave (FMCW) wireless local positioning. The transceiver includes four switchable receiving channels, one transmitting channel and local-oscillator generation circuitries. Several power-saving techniques are implemented, such as switch channel and adaptive mixer biasing. The design aspects of the low-power circuit blocks and integration considerations are presented in details. The integrated transceiver has a chip area of only 2.2 mm × 1.7 mm. In transmitting mode the transceiver achieves an output power of 4 dBm and phase noise of −90 dBc/Hz at 1 MHz, while consuming 75 mW power consumption under 1.5 V power supply. In switch-channel receiving mode the transceiver demonstrates 31 dB gain and 6 dB noise figure with 65 mW power consumption. The transceiver measurements compare well with the simulated results and achieve state-of-the-art performance with very low-power consumption.BMBF, 16SV3654, Low Power Wireless Sensor Network with Localisation (LOWILO

Development of polyaniline microarray electrodes for cadmium analysis

Disposable screen-printed electrodes (SPCE) were modified using a cosmetic product to partially block the electrode surface in order to obtain a microelectrode array. The microarrays formed were electropolymerized with aniline. Scanning electron microscopy was used to evaluate the modified and polymerized electrode surface. Electrochemical characteristics of the constructed sensor for cadmium analysis were evaluated by cyclic and square-wave voltammetry. Optimized stripping procedure in which the preconcentration of cadmium was achieved by depositing at –1.20 V (vs. Ag/AgCl) resulted in a well defined anodic peak at approximately –0.7 V at pH 4.6. The achieved limit of detection was 4 × 10−9 mol dm−3. Spray modified and polymerized microarray electrodes were successfully applied to quantify cadmium in fish sample digests

Molecular imprinted nanoelectrodes for ultra sensitive detection of ovarian cancer marker

The relentless discovery of cancer biomarkers demands improved methods for their detection. In this work, we developed protein imprinted polymer on three-dimensional gold nanoelectrode ensemble (GNEE) to detect epithelial ovarian cancer antigen-125 (CA 125), a protein biomarker associated with ovarian cancer. CA 125 is the standard tumor marker used to follow women during or after treatment for epithelial ovarian cancer. The template protein CA 125 was initially incorporated into the thin-film coating and, upon extraction of protein from the accessible surfaces on the thin film, imprints for CA 125 were formed. The fabrication and analysis of the CA 125 imprinted GNEE was done by using cyclic voltammetry (CV), differential pulse voltammetry (DPV) and electrochemical impedance spectroscopy (EIS) techniques. The surfaces of the very thin, protein imprinted sites on GNEE are utilized for immunospecific capture of CA 125 molecules, and the mass of bound on the electrode surface can be detected as a reduction in the faradic current from the redox marker. Under optimal conditions, the developed sensor showed good increments at the studied concentration range of 0.5–400 U mL−1. The lowest detection limit was found to be 0.5 U mL−1. Spiked human blood serum and unknown real serum samples were analyzed. The presence of non-specific proteins in the serum did not significantly affect the sensitivity of our assay. Molecular imprinting using synthetic polymers and nanomaterials provides an alternative approach to the trace detection of biomarker proteins

Broadly Neutralizing Influenza Hemagglutinin Stem-Specific Antibody CR8020 Targets Residues that Are Prone to Escape due to Host Selection Pressure

Broadly neutralizing antibodies (bNAb) that target a conserved region of a viral antigen hold significant therapeutic promise. CR8020 is a bNAb that targets the stem region of influenza A virus (IAV) hemagglutinin (HA). CR8020 is currently being evaluated for prophylactic use against group 2 IAVs in phase II studies. Structural and computational analyses reported here indicate that CR8020 targets HA residues that are prone to antigenic drift and host selection pressure. Critically, CR8020 escape mutation is seen in certain H7N9 viruses from recent outbreaks. Furthermore, the ability of the bNAb Fc region to effectively engage activating Fcγ receptors (FCγR) is essential for antibody efficacy. In this regard, our data indicate that the membrane could sterically hinder the formation of HA-CR8020-FcγRIIa/HA-IgG-FcγRIIIa ternary complexes. Altogether, our analyses suggest that epitope mutability and accessibility to immune complex assembly are important attributes to consider when evaluating bNAb candidates for clinical development.National Institutes of Health (U.S.) (Merit Award R37 GM057073-13)Singapore. National Research Foundation (Singapore-MIT Alliance for Research and Technology

Intelligent approach on sensorless control of permanent magnet synchronous generator

In this paper, a standalone permanent magnet synchronous generator (PMSG) system is designed to generate power at maximum power point (MPP). The variable speed operation of wind energy conversion system consists of PMSG, controlled rectifier and voltage source inverter co to the load. Proportional integral (PI), sliding mode (SM), and feed forward neural network (FFNN) control strategies are applied in field oriented control (FOC) at generator side converter. A comparative study on power generated at maximum power point (MPP) is done with these controllers using simulation. Hill climb search (HCS) method is applied to attain MPP. Load side inverter control strategy involves the PI and SM controllers in order to maintain the unity power factor and to control the active and reactive power for nonlinear load. The control strategies are modelled and simulated with MATLAB/Simulink. The effectiveness of proposed control method is demonstrated using simulation results

Electroanalysis of urinary L-dopa using tyrosinase immobilized on gold nanoelectrode ensembles

The performance of an amperometric biosensor constructed by associating tyrosinase (Tyr) enzyme with the advantages of a 3D gold nanoelectrode ensemble (GNEE) is evaluated in a flow-injection analysis (FIA) system for the analysis of l-dopa. GNEEs were fabricated by electroless deposition of the metal within the pores of polycarbonate track-etched membranes. A simple solvent etching procedure based on the solubility of polycarbonate membranes is adopted for the fabrication of the 3D GNEE. Afterward, enzyme was immobilized onto preformed self-assembled monolayers of cysteamine on the 3D GNEEs (GNEE-Tyr) via cross-linking with glutaraldehyde. The experimental conditions of the FIA system, such as the detection potential (−0.200 V vs. Ag/AgCl) and flow rates (1.0 mL min−1) were optimized. Analytical responses for l-dopa were obtained in a wide concentration range between 1 × 10−8 mol L−1 and 1 × 10−2 mol L−1. The limit of quantification was found to be 1 × 10−8 mol L−1 with a resultant % RSD of 7.23% (n = 5). The limit of detection was found to be 1 × 10−9 mol L−1 (S/N = 3). The common interfering compounds, namely glucose (10 mmol L−1), ascorbic acid (10 mmol L−1), and urea (10 mmol L−1), were studied. The recovery of l-dopa (1 × 10−7 mol L−1) from spiked urine samples was found to be 96%. Therefore, the developed method is adequate to be applied in the clinical analysis