Temperature-Dependent Performance of Printed Field-Effect Transistors with Solid Polymer Electrolyte Gating

Printable, physical, and air-stable composite solid polymer electrolytes (CSPEs) with high ionic conductivity have been established as a suitable alternative to standard dielectric gate insulators for printed field-effect transistors (FETs) and logics. We have performed a stress and temperature stability study involving several CSPEs. Mechanical tensile and shear tests have been performed to determine the physical condition of CSPEs. A comprehensive temperature dependent study has been conducted within the working temperature range which electric double layer (EDL) capacitors or CSPE-gated FETs may typically experience during their lifetime. Moreover, calorimetric measurements have been performed to investigate the CSPEs stability, especially at low temperatures. Mechanical characterizations have shown tensile strength and shear modulus of the material that is typical for solid polymer electrolytes while DSC measurements show no change in the physical state within the measured temperature range. An expected increase in ionic conductivity of the CSPEs of nearly 1 order of magnitude has been observed with an increase in temperature, while an anomalous positive temperature relationship to EDL capacitance has also been noticed. Interestingly, the transistor performance characteristics, namely, on-current and threshold voltage, are found to be quite independent of the temperature, thus ensuring a large and stable operation temperature window for CSPE-gated FETs. The other parameters, subthreshold slope and the device mobility, have varied following the classical semiconductor behavior. In fact, the present study not only provides a detailed understanding of temperature dependence of the CSPE-gated FETs but also offers an insight into the physical and electrical properties of the CSPEs itself. Therefore, these results may very well help to comprehend and improve EDL capacitors, supercapacitors, and other devices that use CSPEs as the active material

Electrolyte-Gated, High Mobility Inorganic Oxide Transistors from Printed Metal Halides

Inkjet printed and low voltage (≤1 V) driven field-effect transistors (FETs) are prepared from precursor-made In₂O₃ as the transistor channel and a composite solid polymer electrolyte (CSPE) as the gate dielectric. Printed halide precursors are annealed at different temperatures (300–500 °C); however, the devices that are heated to 400 °C demonstrate the best electrical performance including field-effect mobility as high as 126 cm² V^–1 s^–1 and subthreshold slope (68 mV/dec) close to the theoretical limit. These outstanding device characteristics in combination with ease of fabrication, moderate annealing temperatures and low voltage operation comprise an attractive set of parameters for battery compatible and portable electronics

High-Performance All-Printed Amorphous Oxide FETs and Logics with Electronically Compatible Electrode/Channel Interface

Oxide semiconductors typically show superior device performance compared to amorphous silicon or organic counterparts, especially when they are physical vapor deposited. However, it is not easy to reproduce identical device characteristics when the oxide field-effect transistors (FETs) are solution-processed/printed; the level of complexity further intensifies with the need to print the passive elements as well. Here, we developed a protocol for designing the most electronically compatible electrode/channel interface based on the judicious material selection. Exploiting this newly developed fabrication schemes, we are now able to demonstrate high-performance all-printed FETs and logic circuits using amorphous indium–gallium–zinc oxide (a-IGZO) semiconductor, indium tin oxide (ITO) as electrodes, and composite solid polymer electrolyte as the gate insulator. Interestingly, all-printed FETs demonstrate an optimal electrical performance in terms of threshold voltages and device mobility and may very well be compared with devices fabricated using sputtered ITO electrodes. This observation originates from the selection of electrode/channel materials from the same transparent semiconductor oxide family, resulting in the formation of In–Sn–Zn–O (ITZO)-based-diffused a-IGZO–ITO interface that controls doping density while ensuring high electrical performance. Compressive spectroscopic studies reveal that Sn doping-mediated excellent band alignment of IGZO with ITO electrodes is responsible for the excellent device performance observed. All-printed n-MOS-based logic circuits have also been demonstrated toward new-generation portable electronics