Design und Evaluation von Hardware-Architekturen zur Powerline-basierten Kommunikation unter extremen Umweltbedingungen

Moderne elektronische Geräte setzten vermehrt auf den Austausch von Informationen mit dem Benutzer oder einem Online-Dienst des Herstellers, wie zum Beispiel im Smart Home, der Staubsauger-Roboter oder die Waschmaschine. Die Verbindung erfolgt zumeist über drahtlose Kommunikation zum Beispiel auf dem 2,4 GHz-Funkkanal, welcher gerade in dicht besiedelten Städten teilweise schon überlastet ist. Eine Alternative bietet die drahtgebundene Kommunikation über die Stromversorgungsleitung, auch Powerline-Kommunikation genannt. Hierbei werden die Informationen auf freie Frequenzbänder oberhalb der Netzfrequenz moduliert und konkurrieren dabei nur mit den anderen Teilnehmern des eigenen Stromnetzes. Ein Problem bei dieser Art der Kommunikation ist der Übetragungskanal, der nicht für eine hochfrequente Übertragung ausgelegt ist und starke Störungen durch Lastwechsel oder Reflexionen an Impedanzsprüngen erzeugt. Um diese Störungen zu kompensieren verwenden moderne Powerline-Kommunikationsstandards robuste Kanalkodierverfahren, um Fehler in den übertragenen Informationen empfangsseitig korrigieren zu können. Auf Grund dieser robusten Fehlerkorrketurverfahren, eignen sich diese Standards auch für die Kommunikation unter extremen Umweltbedingungen in der Tiefenbohrtechnik. Dabei befinden sich die elektronischen Komponenten entlang der letzten 100 m des Bohrstrangs mehrere Kilometer tief unter der Erde, wo Umgebungstemperaturen mehr als 150 °C, Drücke bis 207 MPa und mechanische Schocks auftreten. Diese extremen Umweltbedingungen haben sowohl Einfluss auf die elektronischen Komponenten, als auch auf den Übetragungskanal der Powerline-Kommunikation selbst. In dieser Arbeit wird erstmalig eine Entwurfsraumexploration für hochtempteraturfeste Hardware-Plattformen eines Breitband-Powerline-Kommunikationssystems durchgeführt. Dabei wird ein Abtausch zwischen Durchsatz, Flexibiltät und Hardware-Ressourcen aufgezeigt, der verschiedene Pareto-optimale Punkte enthält. Diese Pareto-optimalen Punkte umfassen sowohl Prozessor-basiere Plattformen, als auch eine dedizierte Implementierung. Die dedizierte Implementierung wird anschließend in einer FPGA-basierten Emulationen bezüglich Durchsatz, Latenz und Skalierbarkeit des Netzwerkes evaluiert und optimale Konfigurationen aufgezeigt. Abschließend wird diese optimale Konfiguration für die Fertigung als Chip in einer Hochtemperaturtechnologie vorbereitet. Der gefertigte Chip wird auf einer hochtemperaturfesten Leiterplatte in einer Klimakammer unter extremen Umweltbedingungen verifiziert und evaluiert. Die Ergebnisse zeigen eine geringe Leistungsaufnahme und eine stabile Kommunikation mit geringen Paketverlustraten bis zu einer Sperrschichttemperatur von 220 °C. Die Messungen zeigen einen linearen Abtausch zwischen Spannungsversorgung und Stabilität der Kommunikation von 7 mW/°C. Damit erweitert diese Arbeit den aktuellen Stand der Forschung um den ersten Breitband-Powerline-Kommunikation-Chip, der unter extremen Umweltbedingungen evaluiert und charakterisiert wurde

A Case Study on Multi-Softcore Aided Hardware Architectures for Powerline MAC-Layer

Powerline communication is a promising technology for connecting Internet of Things (IoT) applications, where devices have strict limitations regarding available installation space and power dissipation. Especially the wiring of these devices benefits from not having additional cables for network connection. Thus, saving costs and additional installation effort. In this paper a very resource-efficient implementation of a HomePlug 1.0.1 [5] compatible powerline MAC layer, which is used to control the data flow and link status of a powerline connection, is presented. The MAC layer is implemented in two variants, using state machines and softcore processors. A comparison of the two approaches shows that the softcore design used up to 78 % less FPGA ressources and is superior in terms of flexibility and maintainability

Powerline Communication System-on-Chip in 180 nm Harsh Environment SOI Technology

Broadband powerline communication systems using Orthogonal Frequency Division Multiplexing (OFDM) can utilize existing power lines to transmit data packets alongside power distribution. Recent standards focus towards high speed multi-media in-house streaming. With improvements towards robustness and throughput new standards increase the speed and reliability of in-house powerline systems. A very different approach is the use of powerline communication systems in a deep drilling environment where temperatures of more than 150°C and pressure levels up to 30 000 psi are present. Typical applications in this environment usually do not require more than several kbit/ys per node and are more reliant on a stable and continuous connection. Here, a powerline communication system can reduce the amount of wiring needed and increase communication robustness significantly. This work provides a harsh environment suitable, reliable and standard compliant communication ASIC that is manufactured in XFAB 180 nm Silicon-On-Insulator (SOI) technology allowing operating temperatures of up to 175°C. The die size is 5.25 mm x 5.25 mm and contains a complete Homeplug 1.0 communication stack with an environment for boot, interfacing and debugging. The data rate is as high as 6.1 Mbit/s using the fastest transmission mode and reaches the theoretical maximum of 0.55 Mbit/s in the robust OFDM (ROBO) mode which is of particular interest for harsh environment applications. To the best of the authors knowledge, this is the first OFDM-based powerline communication ASIC which is particularly designed for harsh environment.© 2021 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works

Evaluation of Different Processor Architecture Organizations for On-Site Electronics in Harsh Environments

Microcontrollers to be used in harsh environmental conditions, e.g., at high temperatures or radiation exposition, need to be fabricated in robust technology nodes in order to operate reliably. However, these nodes are considerably larger than cutting-edge semiconductor technologies and provide less speed, drastically reducing system performance. In order to achieve low silicon area costs, low power consumption and reasonable performance, the processor architecture organization itself is a major influential design point. Parameters like data path width, instruction execution paradigm, code density, memory requirements, advanced control flow mechanisms etc., may have large effects on the design constraints. Application characteristics, like exploitable data parallelism and required arithmetic operations, have to be considered in order to use the implemented processor resources efficiently. In this paper, a design space exploration of five different architectures with MIPS- or ARM-compatible instruction set architectures, as well as transport-triggered instruction execution is presented. Using a 0.18 μ m SOI CMOS technology for high temperature and an exemplary case study from the fields of communication, i.e., powerline communication encoder, the influence of architectural parameters on performance and hardware efficiency is compared. For this application, a transport-triggered architecture configuration has an 8.5× higher performance and 2.4× higher computational energy efficiency at a 1.6× larger total silicon area than an off-the-shelf ARM Cortex-M0 embedded processor, showing the considerable range of design trade-offs for different architectures.publishedVersionPeer reviewe

Design and Evaluation of a 180 nm Powerline Communication ASIC for Harsh Environment

Modern complex drilling systems contain communication nodes like sensors, actuators, and controllers, spread along the lower end of a drill string. Here, temperatures of more than 150 °C and pressure levels up to 200 MPa are present. These environmental conditions and mechanical shocks, are extremely challenging for the reliable use of electronic components. A powerline communication system is designed and evaluated to establish a robust communication channel with low amounts of wiring. This system can operate on highly distorted physical transmission channels by adding redundancy at the sender that can then be used to correct errors at the receiver. In order to synchronize the real-time clocks among different powerline stations, a new preamble extension approach that enables precise time synchronization between multiple bus nodes is added. After design and verification, this system was manufactured in XFAB 180 nm Silicon-On-Insulator (SOI) technology allowing operating temperatures of up to 175 °C. The die size is 5.25 mm × 5.25 mm and contains a complete HomePlug 1.0 communication stack with an environment for boot, interfacing, and debugging. Its data rate reaches 6.1 Mbit/s using the fastest transmission mode and the theoretical maximum of 0.55 Mbit/s in the robust OFDM (ROBO) mode, which is of particular interest for harsh environment applications. After verifying the fabricated die, a Printed Circuit Board (PCB) for climate chamber evaluation was designed and fitted. Measurements in this chamber carried out a maximum ambient temperature of 190 °C for communication with a minimum self-heating of the die of 20 °C measured at room temperature. In combination, this is 35 °C above the specification of the technology process. The timing synchronization evaluation showed a precision of 55.6 ns over the temperature range from -30 °C to 185 °C, which is as low as 1.5 clock cycles. Power measurements of up to 190 °C have shown an average power consumption increase of only 63μW/K below 150 °C and a maximum increase of 394μW/K above 150 °C. To the best of the authors’ knowledge, this is the first high-temperature evaluation of a powerline communication ASIC, which is particularly designed for a drilling system's harsh environment

Evaluation of Different Processor Architecture Organizations for On-Site Electronics in Harsh Environments

Microcontroller units used in harsh environmental conditions are manufactured using large semiconductor technology nodes in order to provide reliable operation, even at high temperatures or increased radiation exposition. These large technology nodes imply high gate propagation delays, drastically reducing the system’s performance. When reducing area costs and power consumption, the actual processor architecture becomes a major design point. Depending on the application characteristics (i.e., inherent data parallelisms, type of arithmetic,..), several parameters like data path width, instruction execution paradigm, or other architectural design mechanisms have to be considered. This paper presents a design space exploration of five different architectures implemented for a 0.18µm SOI CMOS technology for high temperature using an exemplary case study from the fields of communication, i.e., Reed-Solomon encoder. For this algorithm, an application-specific configuration of a transport-triggered architecture has 37.70x of the performance of a standard 8-bit microcontroller while the silicon area is increased by 4.10x.acceptedVersionPeer reviewe