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Aggressive SiGe Channel Gate Stack Scaling by Remote Oxygen Scavenging: Gate-First pFET Performance and Reliability Remotely M-doped TiN La-based cap O Biaxially strained SiGe Remotely M-doped TiN Al 2 O 3 cap (optional) O Si nFET pFET Si cap (optional) S

We demonstrate that aggressive gate dielectric scaling in hafnium-based high-k/metal gate p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) with biaxially strained silicon germanium channels can be achieved in gate-first integration via remote interfacial SiO 2 scavenging by metal-doped titanium nitride gates. An inversion thickness of 0.86 nm is reached, corresponding to an equivalent oxide thickness (EOT) of 0.45-0.5 nm. Interlayer-scaling-induced threshold voltage increase and hole mobility reduction are studied in detail. We further establish an exponential interlayer thickness dependence of negative bias temperature instability (NBTI). Previously shown to be effective for nFETs, remote oxygen scavenging is an attractive scaling option for dual-channel CMOS. © 2012 The Electrochemical Society. [DOI: 10.1149/2.005302ssl] All rights reserved. Biaxially strained silicon germanium channels (cSiGe) epitaxially grown on silicon have recently received much attention for their ability to reduce the often undesirably high threshold voltage (V t ) of hafnium-based high-k/metal gate (HKMG) p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs or pFETs). 1-5 They are typically combined with Si channel nFETs. In order for such dual-channel complementary MOS (CMOS) to be a viable option for future technology nodes requiring continued reductions in equivalent oxide thickness (EOT), simultaneous gate dielectric scaling for both nFETs and pFETs has to be achieved. We have previously shown that aggressive gate dielectric scaling in Si channel nFETs can be achieved in gate-first integration via remote interfacial SiO 2 layer ('interlayer') scavenging by TiN gate electrodes doped with high-oxygen-affinity metals. 6-8 Herein, we demonstrate that the same approach is viable for SiGe channel pFETs. We then use this scavenging approach to establish quantitative guidelines on interlayer-scaling-induced pFET V t increase, hole mobility reduction, and negative bias temperature instability (NBTI) degradation. Experimental Planar transistors were fabricated in a gate-first process flow, as follows ( • C rapid thermal anneal (RTA) for dopant activation, salicide source/drain metallization, and a final forming gas anneal (FGA) or special cSiGe anneal. 1 While we report data from planar devices, given a sufficiently conformal gate electrode the remote oxygen scavenging approach is expected to be viable for FinFET or Tri-Gate devices as well. Results and Discussion Exemplary transmission electron microscopy (TEM) images of Sicapped low-Ge-content cSiGe pFETs with Al 2 O 3 cap z E-mail: [email protected] capacitance equivalent thickness in inversion ('inversion thickness', T inv ) from 1.41 to 0.86 nm Comparing cSiGe devices with the same Ge content but different Si cap thickness (regular, thin, none) at a given amount of M doping, the T inv data in It has been reported that T inv of Si-capped SiGe channel transistors increases with increasing Si cap thickness, due to the formation of a SiGe quantum well for holes, i.e. a buried channel. 2,9 Our data show no such T inv increase from thin to regular Si caps Finally, since Si caps probably can only prevent regrowth while they are still intact, we note that interlayer regrowth on uncappe